I am using 32bits slave FIFO sychronous mode. I need to send 8KB data to PC, and I divided them into 16 packets, each packet is 128*32bits (512B), at the end of each packet, there is a packet_end signal. The endpoint buffer size was set to 1024B and I keep monitoring the full flag to make sure there is no overflow. However, I can not receive the whole 8KB data in the USB control center. Instead I only got 2342~2396B, each time different. Can anybody tell me what may be the proper problem? I am sure FPGA has write the data into CYUSB3014, and there is no overflow.
FX3 will split the data to packets of maximum packet size and send it to the host. You don't have to assert the packet_end at the end of each 512.
With regards to missing data, do you see a pattern in the missing data i.e. first 2k is being received, alternate packets of 512 being received etc etc?
Yes, I have checked the data pattern. The first 512B was received correctly, then 272B missing, then 240B received, then 272B missing, then ...... That's the law. Can you see the reason?
For correct stopping at buffer full also in packet end mode, you have to monitor the partial full flag (to remove the 3 clock latency) and also the normal full flag. Wrting short packets with packet end to the slave fifo does not set the partial full flag if all buffers are full. This case is only hadled by the normal full flag. Maybe this is your problem.
How to use both normal full flag and partial flag at the same time? Now I am using flag_a as read thread empty flag, and flag_b as write thread full flag. During the data transfering, I was keep monitoring the full flag, even if considering the 3 clock cycle latency, I shouldn't lose so much data.
Generally if I want to transfer mass data from FX3 to PC, how should I organize my data packets? For example, I used thread 0 as the write channel and set the socket buffer size to 2048B. Each time I write 1024B data into the buffer with a packet_end signal. Is this method alright? Or there is a best strategy to use slave FIFO to transfer mass data?
If you watch the normal full flag the problem schould be another. Our system requests data from the hardware and can set the packet end in the read request command. So we are able to transfer data blocks as large as possible and set the packet end to the logical end of a data block. There is no need to mark every packet with packet end. AFAIK you cannot set the packet end on the last word of a full packet, there will be data loss. So I set the packet end always some cycles after the last word. In the host software there may be a zero length packet, but this is no problem, the protocol decoder in the host software can manage this. By the way: we use WinUSB driver. At the moment I run a hardware based on the DVK connected to our "old" hardware replacing the FX2 directly. There was no change needed in the host software. I only had to change the FPGA design slightly. It runs stable for hours with different data block lengths.
Hi Chris R. ,I want to know you how to avoid the 3 clock latency
Can you give me more details to configure the GPIF about partril flag.
jogn: I described this in another forum thread here.
To the data loss: Today I made som tests and figured out, that there is a big difference between FX2 and FX3. If I fill the buffer with exact the max. packet size, I only can get the data if I request the exact size from the device. If I request more data, the FX3 hangs and has to be reseted. In the FX2 this was possible using packet end some cycles after the last word and enabling ZLPs. The same technique does not work correctly on FX3.