Interconnection board

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MaMa_4520856
Level 4
Level 4
25 replies posted 25 sign-ins 10 replies posted

Hello,

I'm using cyusb3kit-001 with xilinx FPGA (Spartan SP605 XC6SLX45T) and I'm trying to implement syncADMux on my FPGA and CYUSB3ACC-002 interconnection board to connect them ; but I cant find anywhere how to set up pins in  FPGA for specific GPIO Ports

I have tried using AN65974 firmware but its designed for different device where pins have different names.

As per my understanding the signals showed in

https://www.cypress.com/file/136056/download

are same (for my use I need DQ 00:15, PCLK, CTL 0:2, and for GPIO[27] - cant find signal name)

below I'm attaching screen from GPIF designer

Can you please show me where can I find pins in FPGA that are connected to those signals

pastedImage_3.png

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1 Solution
JayakrishnaT_76
Moderator
Moderator
Moderator
First question asked 1000 replies posted 750 replies posted

Hello,

According to my understanding, you would like to know which pin of FPGA is connected to GPIO 27 of FX3. Please confirm if my understanding is wrong.

GPIO 27 is CTL[10] from FX3 datasheet. You can find this in page 15 of FX3 datasheet (link given below).

https://www.cypress.com/file/140296/download

Now, in order to find to which pin of FPGA, CTL[10] is routed to, you need to check the schematics of CYUSB3ACC-002 interconnection board. You can download it from the following link:

https://www.cypress.com/documentation/development-kitsboards/cyusb3acc-002-fmc-interconnect-board-ez...

According to the schematics, CTL10 goes to G34 of J3C. Upon connecting the FPGA to the interconnect board, that pin of FPGA connected to G34 should provide the ADV signal.

Please let me know if you have more queries on this.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna

View solution in original post

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3 Replies
JayakrishnaT_76
Moderator
Moderator
Moderator
First question asked 1000 replies posted 750 replies posted

Hello,

According to my understanding, you would like to know which pin of FPGA is connected to GPIO 27 of FX3. Please confirm if my understanding is wrong.

GPIO 27 is CTL[10] from FX3 datasheet. You can find this in page 15 of FX3 datasheet (link given below).

https://www.cypress.com/file/140296/download

Now, in order to find to which pin of FPGA, CTL[10] is routed to, you need to check the schematics of CYUSB3ACC-002 interconnection board. You can download it from the following link:

https://www.cypress.com/documentation/development-kitsboards/cyusb3acc-002-fmc-interconnect-board-ez...

According to the schematics, CTL10 goes to G34 of J3C. Upon connecting the FPGA to the interconnect board, that pin of FPGA connected to G34 should provide the ADV signal.

Please let me know if you have more queries on this.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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Hello,

just to be clear Have I correctly assigned GPIO signals to FPGA PINS?

pastedImage_1.png

Regards,

Mateusz

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Hello,

I see that DQ15 is incorrectly mapped as H26. It seems like a typing mistake. But it goes to H28. All the remaining pairs are correctly identified.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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