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USB Superspeed Peripherals

Anonymous
Not applicable

Hello,

   

In my FX3 firmware we have an issue with Slave FIFO data correctness. We feel that the reason for the data correctness issue is that the PC is not starting the transfer quickly enough. Therefore, we would like to visualize the time we got USB IN transfer and compare that with FPGA signals.

   

Therefore, I want to toggle an IO pin when the USB IN packet reaches the FX3. Then I can trigger to that signal and determine the time between USB IN arrival and FPGA data arrival.

   

Or is there any better way to do this?

   

We have 128 x 1024 buffers configured for DMA channel between Thread0 and USB endpoint 0x82. We have 2kB FIFO in FPGA. When we read data from the PC, we can see that once we got 130kB (which is 128kB + 2kB FPGA buffer) we lose some amount of data. After that rest of the data received in that transfer is correct. 

   

For example: 

   

If I read 10MB of data using XferData function in PC side. First 130kB of buffer is correct. Then we lose some data. After that the rest of 10MB data is correct. 

   

We believe that the reason for this is that eventhough we call XferData function in PC, it takes some considerable time to reach the IN transfer to FX3. Because of that the FPGA FIFO is overflowed.

   

Please let me know the way to visualize when the IN transfer reaches the FX3.

   

Thank you.

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2 Replies
Anonymous
Not applicable

How many buffers are you using? Are you using a single buffer of 128 K? Can you create a technical support case for this?

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Anonymous
Not applicable

I'm using 128 buffers with 1024Bytes in each one of them.

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