In my design, CYUSB3014 will be connected with a FPGA that plays a role of slave. The 3014 is a master and it could give a serial signals(OE REN and WEN) to the FPGA in order to exchange data.
For example, REN and OE are coming out from 3014 to 'tell' the FPGA 'I will collect data later', and then the FPGA will output a serial of data via databus in burst. Finally, the 3014 will receive the data and send them back to PC.
But when I follow the idea, firstly I found that OE and WE (special function checkbox) are still input regardless of whether master mode is selected. For this reason, I give up the special function signals and create three output signals, name them 'OE','WEN' and 'REN'. Secondly when I start to design 'equation entry' , I face the problem that only input signals can be selected. While the 3014 should output the three signals instead of 'listen' from perpherals, because it is master.
On the other hand, all templates of supplied interfaces in the sofeware are based on slave mode, therefore I am still confused and I really hope to have a example for my puzzle.