FX3 and GPIF-II Designer Timing

[AlEr_4025481]

Hi,

I made a simple GPIF-II design to read one 16-bit word to processor socket when external WE signal turns from low to high. Is timing tab for my design correct? I was expecting DATA_IN operation should happen at the beginning of STATE1, but not STATE0.  My design is attached below.

[AliAsgar · Accepted solution]

Hello,

The timing diagram in GPIF designer tool is not reliable. Kindly probe the signals at your end and verify.

Best Regards,
AliAsgar