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Hi.
Now I am trying to implement Slavefifo Bulk In mode woth FPGA and FX3 Kit.
I'm followed the AN65974 example code.
In my case, I use 8bit data width. and use 100Mhz pclk from FPGA into FX3 boards.
The Problem is the slavefifo does not work.
So I need help with any hint. Please. Does anyone know how to fix?
-FPGA code ------------------------------------
always @(posedge pclk or negedge rst)
begin
if(!rst) begin
slcs_n<=1;
slwr_n<=1;
sloe_n<=1;
slrd_n<=1;
pktend_n<=1;
end else begin
slcs_n<=0;
slwr_n<= 0
sloe_n<=1;
slrd_n<=1;
pktend_n<=1;
end
end
always @(posedge pclk or negedge rst)
begin
if(!rst) begin
dq <= 0;
end else begin
dq <= dq+1;
end
end
endmodule
-Firmware code--------
I 've attached the Firmware code in here.
Basically, I followed as follow concept. Please check the Images and firmware code.
BULK IN transfer
BULK IN transfer failed with Error Code:997
What am I supposed to fix my problem to work?
I've already double checked PCLK = 100Mhz, dq is working normaly into the FX3 board.
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Hi,
How long are you transferring the data? Have you stopped transferring as soon as the buffer is filled, by monitoring the flags? If not it will result in PIB Errors getting triggered.
Please take a chipscope trace of Master signals and ensure that they are fine.
Regards,
-Madhu Sudhan
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