According to the documentation ("Designing with the EZ-USB FX3 Slave FIFO Interface"), the propagation delay for the (watermark/ready) flags from the rising edge of the clock is max. 8 ns (tcflg) without specifying a minimum. So one has to assume it can be anywhere between 0 and 8 ns, right? But if correct that would mean that with a 100MHz GPIF-clock which has a period of 10 ns, one only has a 2 ns window to correctly sample the flag values. When eg. interfacing with a FPGA this means it's a "challenge" or it least not very easy to get the timing constraints right to make this reliably work.
Am I correct? And if so: what are the recommendations to do this the proper way?
