I have setup with fx3 connected to the fpga fabric of a xilinx zynq 7000 series chip. I am trying to get bulk streaming in for sending image data from the fpga to the host computer using the fx3.
I am able to send data by using the dma ready flag but certain number of bytes go missing at each transfer. I am guessing it is due to the flag latency.
So I am trying to use the watermark to stop this from happening. I am following the example given in http://www.cypress.com/?rID=51581 (AN65974 slave fifo sync example).
But I am unable to get it working, there is no data received in the host side, I get the following error in the control center
"BULK IN transfer
BULK IN transfer failed with Error Code:997"
So no data is being transfered. Can anyone help me out with this? I can share more of my code if necessary.
Can you please convert the AUTO DMa Channles into the Code to MAnual DMA CHannels and see if the DMA Callback is being triggered on the data arrival?
Please let me know if you need any assistance in this.
- Madhu Sudhan
Thanks for the reply. I was able to solve the problem. When setting the DMA watermark in the fx3 firmware. I had to use a burst length of 16 but had used 1. Changing it solved the problem.
There is problem with watermark level in FX3. I have 16-bit bus width, watermark level is set to 3. When slwr signal is continuous for whole DMA buffer size everything OK. When slwr has transitions to 1 - full flag never goes low. I think some data words were lost. When I decrease watermark level to 2, full flag goes low, but overrun error is reported by PIB callback.