Hai all,
I am working on FX3 cypress. I need to pass the data from Host to External Device (Demod) by using slave FIFO concept but only change is Clock. clock is internal clock.
The GPIF designer as shown in bellow figure.
1.In AN65974 application note given Ready flag takes extra 2 cycle for read transfer from slave FIFO, so that I am using Partial flag as a Data valid signal to Demod device.
2. Read signal is input signal from Demod its tell the BUFFER free in Demod.
3. clock= internal.
4. data bus=16.
water mark value setting: "CyU3PGpifSocketConfigure (0,CY_U3P_PIB_SOCKET_0,0,CyTrue,1);"
GPIF State machine:
Out put wave from:
The above figure shows the output wave from of Read data from Host to Demod. packet size is 64.
* Yellow wave is Partial flag signal.
* Blue colour wave is data bus.
Q1. why Partial Flag is asserted Before data came? in Given AN65974 note 0 cycle of start transfer.
Q2. In Given AN65974 note FULL/EMPTY flag takes 0 clock cycle at start of data transfer and 2 clock cycle for end transfer. But When I use Full/Empty flag it takes 2 extra clock cycle for start data transfer and Why?.
Q3. how to check Read Signal from External device in state machine?.
Q4. AN65974 section 8.3 given 3 formula for water mark calculation I listed below which one is correct.
"When writing from an external master to the synchronous Slave FIFO:
(a) The number of data words that may be written after the clock edge at which the partial flag is sampled low =
watermark x (32/bus width) – 4
2. When reading into an external master from the synchronous Slave FIFO:
(a) The number of data words available for reading (while keeping SLOE# asserted) after the clock edge at which
the partial flag is sampled asserted = watermark x (32/bus width) – 1
(b) There is already two-cycle latency from SLRD# to the data. Hence, the number of cycles for which SLRD#
may be kept asserted after the clock edge at which the partial flag is sampled asserted = watermark x (32/bus
width) –3."
Thank you.
Best Regards,
Thrimurthi M
