Complex GPIO pin confguration question

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JEv_295166
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The KB article here http://www.cypress.com/knowledge-base-article/gpio-configuration-fx3#comment-418171 states that gpioComplexEn[0] and gpioComplexEn[1] must have a bitmask applied in order to be able to set up specific pins in complex mode.

   

However it fails to say how the bitmask bits map onto the various GPIO pins. 

   

For example I have a GPIF2 design using 8 bit transfers. I'd like to use CTL[0] (GPIO17) as a clock. As far as I can tell, this would mean applying a bitmask of 0x20000 to gpioComplexEn[0]. However this seems to cause the FX3 to fail right from the get-go.

   

Does anyone have a working example and (ideally) a better explanation of these masks? Even the API documentation is extremely light on detail.

   

TAIA

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