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Can't send valid address to fx3 device

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Can't send valid address to fx3 device

MaMa_4520856
Level 4
Level 4
25 replies posted 25 sign-ins 10 replies posted
‎Aug 12, 2020 04:55 AM
‎Aug 12, 2020 04:55 AM
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Hello,

I am trying to send valid address to my fx3 device.Firmware I use is AN65974, and the state machine is SyncADMUx.  The board I'm using is cyusb3kit-001, and I'm using xilinx spartan SP605 conifgured as master.

The fx3 device is stuck at IDLE state, sending data over USB Control Center doesn't help.

In the project manager (part of xilinx web pack) I've tried to set data but to uninitialized (U value) and after this i cant change to ADDR state from IDLE.

below I'm sending fragment of my vhdl code

In attachment I'm sending my project for fx3 board (USBBulkSourceSink.rar) and for fpga board (SyncADMux.rar)

pastedImage_0.png

Regards,

Mateusz

USBBulkSourceSink.rar
SyncADMux.rar
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Re: Can't send valid address to fx3 device

Rashi_Vatsa
Moderator
Moderator
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5 likes given 500 solutions authored 1000 replies posted
In response to MaMa_4520856
‎Aug 17, 2020 11:36 PM
‎Aug 17, 2020 11:36 PM
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Hello Mateuz,

It seams like it transition to other states but with some kind of error (when I change CE# signal to high value it returns to IDLE state without fail or any error)

>> For transition to IDLE state from any of the three WRITE states will be done of any of the CE or WE is asserted. As DMA buffer size (in the firmware) is 1024. You can write 1024 bytes to one DMA buffer. As you have two DMA buffers for P to U channel, the socket will switch the buffer once one DMA buffer is full. The buffer switching will take some time meanwhile the WE should be high to avoid overrun.

Please let me know how much data is sent from USB to PIB/GPIF which is then read.

The default state machine will drive 16-bit words/clock cycle from the DMA buffer. From the firmware i find that the DMA buffer size is 1024 so if  the data read (by enabling !OE) is more than the data present in DMA buffer then CYU3P_PIB_ERR_THR0_RD_UNDERRUN  event is seen.

So, please check if the OE is asserted for the appropriate number of clock cycles such that the master asks for the same amount of data present in DMA buffer.

Please let me know if any queries on this

Regards,

Rashi

Regards,
Rashi

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