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USB Superspeed Peripherals

MaMa_4520856
New Contributor II

Hello,

I am trying to send valid address to my fx3 device.Firmware I use is AN65974, and the state machine is SyncADMUx.  The board I'm using is cyusb3kit-001, and I'm using xilinx spartan SP605 conifgured as master.

The fx3 device is stuck at IDLE state, sending data over USB Control Center doesn't help.

In the project manager (part of xilinx web pack) I've tried to set data but to uninitialized (U value) and after this i cant change to ADDR state from IDLE.

below I'm sending fragment of my vhdl code

In attachment I'm sending my project for fx3 board (USBBulkSourceSink.rar) and for fpga board (SyncADMux.rar)

pastedImage_0.png

Regards,

Mateusz

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1 Solution
Rashi_Vatsa
Moderator
Moderator

Hello Mateuz,

It seams like it transition to other states but with some kind of error (when I change CE# signal to high value it returns to IDLE state without fail or any error)

>> For transition to IDLE state from any of the three WRITE states will be done of any of the CE or WE is asserted. As DMA buffer size (in the firmware) is 1024. You can write 1024 bytes to one DMA buffer. As you have two DMA buffers for P to U channel, the socket will switch the buffer once one DMA buffer is full. The buffer switching will take some time meanwhile the WE should be high to avoid overrun.

Please let me know how much data is sent from USB to PIB/GPIF which is then read.

The default state machine will drive 16-bit words/clock cycle from the DMA buffer. From the firmware i find that the DMA buffer size is 1024 so if  the data read (by enabling !OE) is more than the data present in DMA buffer then CYU3P_PIB_ERR_THR0_RD_UNDERRUN  event is seen.

So, please check if the OE is asserted for the appropriate number of clock cycles such that the master asks for the same amount of data present in DMA buffer.

Please let me know if any queries on this

Regards,

Rashi

Regards,
Rashi

View solution in original post

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19 Replies
MaMa_4520856
New Contributor II

I have tried to do this without this if ( data /= "UUUUUUUUUUUUU") but the resoult was i got stuck at ADDR state

Regards,

Mateusz

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Rashi_Vatsa
Moderator
Moderator

Hello Mateusz,

after this i cant change to ADDR state from IDLE.

>> Please confirm that this IDLE state is in the GPIF state machine state. From this, I understand that the state machine is not transitioning to ADDR state and is stuck in the IDLE state. Is that right?

- Please share the debug prints while running the firmware.

- Also, confirm that you use the default SyncADMUx GPIF state machine i.e. without any custom changes done.

- If possible, please probe the CE and ADV lines and share the traces

Regards,

Rashi

Regards,
Rashi
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MaMa_4520856
New Contributor II

Hi Rashi,

I managed to

Below I'm sending debug prints, I managed to change to state to ADDR but cant go anywhere from there, I created boolean local variable and based on its value it changes to read or write states.

I'm using default SyncADMUx GPIF state machine

Unfortunately right now I can't probe signals

pastedImage_0.png

Regards,

Mateusz

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Rashi_Vatsa
Moderator
Moderator

Hello Mateusz,

Please let me know the changes which made the state machine to switch to ADDR state

It seems that the GPIF state machine is stuck at state 2. This can be mainly due to two reason

1) Clock from the master is not stable

2) From ADDR state the GPIF state machine can transition to either READ state or Write_start based on  CE, OV, WR, ADV signals. Please confirm if these signals are asserted (by FPGA) as expected.

Please l confirm that the clock,  CE, OV, WR, and ADV signals are working as expected. As you are using Xilinx FPGA, is it possible to use Integrated Logic Analyzer to probe the signals  (outputs of FPGA)

Regards,

Rashi

Regards,
Rashi
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MaMa_4520856
New Contributor II

Hi Rashi,

It seems that for some reason the WE# and OE# signals are low at the same time is it possible that state machine doesn't know what to do and just stays on ADDR state?

When I'm running simulation it runs as I expect it to do

pastedImage_0.png

Below I'm sending screen from simulation

pastedImage_1.png

Regards

Mateusz

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MaMa_4520856
New Contributor II

Hello Rashi,

I have changed my code in vhdl and assigned OE# WE# and CE# signals to buttons when WE signal is LOW I got those debug prints

pastedImage_0.png

It seams like it transition to other states but with some kind of error (when I change CE# signal to high value it returns to IDLE state without fail or any error)

When from ADDR state i set OE# signal to low i got those debug prints

pastedImage_1.png

It seams like even after those error it changes to READ state between error i got SMState = 0x3

Regards,

Mateusz

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Rashi_Vatsa
Moderator
Moderator

Hello Mateuz,

It seams like it transition to other states but with some kind of error (when I change CE# signal to high value it returns to IDLE state without fail or any error)

>> For transition to IDLE state from any of the three WRITE states will be done of any of the CE or WE is asserted. As DMA buffer size (in the firmware) is 1024. You can write 1024 bytes to one DMA buffer. As you have two DMA buffers for P to U channel, the socket will switch the buffer once one DMA buffer is full. The buffer switching will take some time meanwhile the WE should be high to avoid overrun.

Please let me know how much data is sent from USB to PIB/GPIF which is then read.

The default state machine will drive 16-bit words/clock cycle from the DMA buffer. From the firmware i find that the DMA buffer size is 1024 so if  the data read (by enabling !OE) is more than the data present in DMA buffer then CYU3P_PIB_ERR_THR0_RD_UNDERRUN  event is seen.

So, please check if the OE is asserted for the appropriate number of clock cycles such that the master asks for the same amount of data present in DMA buffer.

Please let me know if any queries on this

Regards,

Rashi

Regards,
Rashi

View solution in original post

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MaMa_4520856
New Contributor II

Hello Rashi,

If I understand you correctly I need to be sure that I folow the timing from  shown below (this timing is from this document https://www.cypress.com/file/139246/download )

for read cycle

pastedImage_1.png

for write cycle

pastedImage_2.png

regards,

Mateusz

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Rashi_Vatsa
Moderator
Moderator

Hello Mateusz,

Yes, you need to follow the timings mentioned in the datasheet.

The error that you mentioned CYU3P_PIB_ERR_THR0_RD_UNDERRUN in the previous post occurs when the data read (by enabling OE for a more than expected clock cycles) by the slave is more than what is available in the DMA buffer.

Please let me know if any queries on this

Regards,

Rashi

Regards,
Rashi
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MaMa_4520856
New Contributor II

Hello,

how do I detect witch traffic I want to use by that I mean the FX3 device sould wait in IDLE state until I initiate transfer from my PC (to read or to write from FPGA Master device)

For example if I want to write some data i initiate transfer from PC and after that FPGA should assert CE and ADV as low, after reading address it should assert ADV as High and then WE as low

To be as much precise as I can I want to set OE value when I want read from FPGA (from PC point of view it will be IN transfer) and WE when i want to write to FPGA (from PC point of view it will be OUT transfer)

In this Document (Getting Started with EZ-USB SUITE FX3 -https://www.cypress.com/file/337011/download ) SECTION 7 it mention that GPIF can send Interrupt signal when USB socket is filled with data if its possible to do it (with basic SYNC ADMUX state machine witch) I use can you send me some kind of guide how to do it

Regards,

Mateusz

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Rashi_Vatsa
Moderator
Moderator

Hello Mateusz,

From the description, I understand that you are asking for some flow control features. Is that right?

If yes, you can use two flags i.e.

DMA Ready flag: This flag can be used by FPGA to know when to start the data transfer i.e. either READ  /WRITE

DMA  Watermark flag: This flag can be used to stop the data transfer based on the watermark value set.

Please refer to section 8 and  table 4 of application note to understand the working of these flags

https://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-inte...

For adding the flow control flags you would need to do changes in GPIF state machine as well as in the firmware.

Please let me know if any questions on this

Regards,

Rashi

Regards,
Rashi
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MaMa_4520856
New Contributor II

Hello Rashi,

back to the underrun error I ensured that my OE signal is asserted for appropriated number of clock, and still got this error, I have tried it on empty DMA buffer and I tried to fill DMA buffer with some data, result are the same.

Every signal for testing purpose are asserted to buttons and if FPGA Master is in the right mode and button is pushed right signal is changing from 1 to 0, it changes from 0 to 1 without need for pushing button

Due to some issues right now I cant probe signals all I can to is to rune simulate in iSim Simulator.

pastedImage_0.png

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Rashi_Vatsa
Moderator
Moderator

Hello Mateusz,

Please let me what is the DMA buffer size that is being used in your firmware and for how many clock cycles is OE and CE asserted for a particular address.

Please refer to the Timing tab of the GPIF Designer Tool and set the appropriate DMA buffer size used in your firmware and choose READ operation. You will get the appropriate timing scenario based on the input and outputs. Please check this timing analysis.

Regards,

Rashi

Regards,
Rashi
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MaMa_4520856
New Contributor II

Hello Rashi,

Dma Buffer size is 1024 bytes

The OE and WE signal are asserted for 3 clock cycles (after 2 clock cycles it expects data to be read or write)

The state machine I use is SyncADMux without any custom changes

Regards

Mateusz

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Rashi_Vatsa
Moderator
Moderator

Hello Mateusz,

Please confirm when do you face the issue of underrun. Is it while transferring the data from USB> PIB (GPIF) or is it while transferring the data from PIB (GPIF) > USB?

Also, let me know whether you have enabled the macro MANUAL in the firmware or are the DMA channels in AUTO mode.

Regards,

Rashi

Regards,
Rashi
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MaMa_4520856
New Contributor II

Hello,

I got this error when asserting OE signal so transfer is from PIB > USB (performing ready from FPGA Master).

DMA channels are in AUTO Mode

Regards,

Mateusz

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Rashi_Vatsa
Moderator
Moderator

Hello Matuez,

In the default syncAdmux GPIF state machine, OE (output enable) signal is used for driving data out of the FX3 i.e. when the transfers are from USB (producer)>PIB(consumer). WE (write enable) need to be asserted to write data to FX3 i.e. the PIB (producer)>UIB channel(consumer).

How do you assert the OE signal from the FPGA? Is it like you count the amount of data to be read is counted on the FPGA and when the count value hits the OE is de-asserted.

As there is some problem in the handshaking between FX3 and FPGA master. You can modify the GPIF state machine to add the DMA flags. For reading the data from FX3 you can check for DMA flags. These flags will let the master know the status of the DMA buffer of FX3. There are two flags: DMA ready flag which will be asserted when the DMA buffer is full (the master can monitor this flag to start the READ( OE can be asserted) and the DMA watermark flag will be asserted when some bytes of data is yet to be read (or the DMA buffer is about to be empty). On monitoring the DMA watermark flag the FPGA master will know after how many cycles the OE has to be de-asserted so that there is no thread underrun error.

You can refer to section 8 of the AN65974 application note to get more details on the working of these flags and how to calculate the watermark value for the watermark flag.

Regards,

Rashi

Regards,
Rashi
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MaMa_4520856
New Contributor II

Hello Rashi,

So in order to write data from PC (producer) to FPGA (customer) Master First I need to assert WE signal to enable write operation in FX3 device and when  I stop writing data i should de-assert the WE signal and assert OE signal (after the rdy signal is de-asserted) in order to perform writing to FPGA (driving data out of the FX3 device).  Similar is for the transfer from FPGA Master (producer) to PC (customer)  first assert WE flag in order to write data from FPGA to FX3 device, the assert OE signal to send data from the FX3 to PC.

Does the DMA Flagas can help me to see witch direction the data flow will be (I men PC>FPGA or PC<FPGA dierctions), because in every case I need to send address to witch I want to read or write data.

Right now I'm focusing on reading and sending only 1 portion of data (16b), but I'll probably follow your advice and make change to add DMA Flags because it'll be a lot easier to see when the DMA buffer is empty

regards,

Mateusz

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Rashi_Vatsa
Moderator
Moderator

Hello Mateusz,

The FPGA/master will assert the OE signal to read data from FX3 (i.e. transferring data from Host to FPGA via FX3). Similarly, WE signal will be asserted by FPGA when data is to be written to FX3 (i.e. transferring data from FPGA to host).

Two flags can be for each channel i.e. 4 flags (Flags ABCD) in total can be used. Two flags (DMA ready flag and watermark flag) for PIB>USB channel and two for USB > PIB channel. But if the address bus width is 8 bits  (as in the default GPIF state machine) these flags won't be available. If 8 bits address bus is used in your application, then FPGA should count the data sent/received and assert the WE/OE signals accordingly.

Regards,

Rashi

Regards,
Rashi
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