Hello,
my application really needs 2.4 Gbps capture over the D-PHY/CSI-2/GPIF/DMA chain, so I absolutely need to cope with 100 MHz capture with the GPIF.
I therefore needed to change the master clock from 384 MHz (= 19.2 MHz * 0x14) to 403.2 MHz (= 19.2 MHz x 0x15), by setting to CyTrue the setSysClk400 field of the clkCfg parameter of the CyU3PDeviceInit function call.
I'm sure that this is working, since after rising the clock speed I'm not suffering any more (silent) FIFO overflows.
Unfortunately I'm experiencing strange code instabilities (random failures of application-level tests that come and go according to apparently non-correlated changes in the CX3's FW code) in that configuration, that I manage to completely resolve in two very different ways:
1) switching back to the 384 MHz master clock (and testing using a lower rate data source)
2) keeping the instruction cache always disabled instead of enabling it at boot time
The first option is not compatible with my 2.4 Gbps requirement, so it is not a real solution, while the second option so far appears to be fine in (sustained) practice, even if quite weird from a theoretical point of view.
Considering that the CX3/FX3 Technical reference Manual seems to forbid the 403.2 MHz setting for the master clock (as a value of 0x14 is mandated for the FBDIV field of the GCTL_PLL_CFG register), I'm concerned that there is some undocumented side-effect of that configuration, possibly affecting the instruction cache functionality.
Any comment from Cypress or other users ?
Let me also ask if an intermediate master clock frequency of 400 MHz could also be obtained, by setting GCTL_PLL_CFG.REFDIV to 6 and GCTL_PLL_CFG.FBDIV to 125.
That would still be in contrast with the Technical Reference Manual and would require overriding what currently implemented in the SDK.
Thanks and best regards, Nicola.
