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hello world,
im having a dvb tuner streaming over fx2lp slave IN to PC application.
when changing tv-channels the fx2lp gets a "hickup" not sending more data to PC.
i am monitoring the EP2STAT reg for EPfull and the EPprogrammable flags.
The FLAGA is output to a Pin CTL0 and toggles nicly when streaming.
Changing channel or turn off streaming gets FLAGA stay high (telling fifo full) and the EPfull bit also is on.
alright, i tryed to reset this situation by doing a FIFO-RESET sequence :
for (i=0;i<20;i++)
{
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions. ie. NAK all transfers
SYNCDELAY; // see TRM section 15.14
EP2CFG = 0x00; //switching to manual mode
SYNCDELAY;
FIFORESET = 0x82; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x82; // reset, FIFO 2
SYNCDELAY; //
EP2CFG = 0xE0; //switching back to auto mode
SYNCDELAY;
FIFORESET = 0x00; // deactivate NAK-ALL, resume normal operation
SYNCDELAY;
}
No chance, the FLAGA and th efull flag stay on, even when tuner is not streaming any more.
this is a beast 😉
Solved! Go to Solution.
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- fx2lp
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Hello,
Please confirm if you are using the default firmware with this application note https://www.cypress.com/documentation/application-notes/an61345-designing-ez-usb-fx2lp-slave-fifo-in... .
If no, please let us know how is the changing of channel or streaming turned off handled by the firmware
Rashi
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Hello,
Please confirm if you are using the default firmware with this application note https://www.cypress.com/documentation/application-notes/an61345-designing-ez-usb-fx2lp-slave-fifo-in... .
If no, please let us know how is the changing of channel or streaming turned off handled by the firmware
Rashi
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i am using the " AN58069 - IMPLEMENTING AN 8-BIT PARALLEL MPEG2-TS INTERFACE USING SLAVE FIFO MODE IN FX2LP"
When i start a TV channel, everything works fine, the FLAGA (telling fifo half full) is toggling nicly.
When i stop the TV channel, the tuner is instructed to stop streaming the mpeg-stream and the mpeg-VALID signal on SLWR goes low, so there is no more input into the fifo.
However, FLAGA stays high, indicating fifo is above half-full, probably because the PC is not reading anymore.
So in this situation i want to reset the FLAGA by doing a EP2 fiforeset.(code above)
But it stays high...?
The reason why i want to reset is, when i re-start the stream afterwards i am getting bad input data or no data at all.
The FLAGA will not toggle anymore, it just stays high. hmm?
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Hi,
Apologies for the delay in the response.
Please let us know the following:
>> In which mode are you using the flags, indexed or fixed?
>> How have you configured the endpoints?
>> What is the polarity of the flags?
It will be better if you can provide the firmware source,
Regards,
Mallika