Hi all,
I have a following problem:
I am using FPGA Spartan 6-cy7c68013a interface. Master FPGA sends the data from 1st to 2048th byte to EP6 (Bulk transfer, slave FIFO, 2048 bytes depth). I wrote a program on Visual Studio that requests the data from cypress EZ-USB device's FIFO.
The problem is that most of the times data packet is right:
1-2-3-4-5-6-7.....-2047-2048.
However, sometimes the format of the packet is wrong, parts of packet are swapped:
430-431-432-.....-2047-2048-1-2-3...428-429.
And the begging data is always random: it can be 430, 110 or anything. But, the cycle is always complete and all the set of data values (from 1 to 1024) is transferred.
What can be the problem? Can anyone help to resolve it?
