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USB Low-Full-High Speed Peripherals

mrmiziev
New Contributor

Hi all,

I have a following problem:

I am using FPGA Spartan 6-cy7c68013a interface. Master FPGA sends the data from 1st to 2048th byte to EP6 (Bulk transfer, slave FIFO, 2048 bytes depth). I wrote a program on Visual Studio that requests the data from cypress EZ-USB device's FIFO.

The problem is that most of the times data packet is right:
1-2-3-4-5-6-7.....-2047-2048.

However, sometimes the format of the packet is wrong, parts of packet are swapped:

430-431-432-.....-2047-2048-1-2-3...428-429.

And the begging data is always random: it can be 430, 110 or anything. But, the cycle is always complete and all the set of data values (from 1 to 1024) is transferred. 

What can be the problem? Can anyone help to resolve it?

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1 Solution
MallikaK_22
Moderator
Moderator

Hi,

Apologies for the delay in response.

Could you please let me know if you are using custom hardware or our DVK? If you are using custom hardware, please share the board schematics.

Regards,

Mallika

 

Mallika

View solution in original post

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2 Replies
mrmiziev
New Contributor

Hi again, maybe my question was too generic, so this time I attach pieces of code.

 

1) The code on Visual Studio, that constantly asking EZ-USB to transfer data and process it. I attach only the part with requesting data, since processing is irrelevant:

while(writtingstarted) // activates with button

if (myDevice != null)
{

      if (myDevice.BulkInEndPt != null)
      {
           int len = 2048;
           byte[] buf = new byte[len];
           myDevice.BulkInEndPt.TimeOut = 100000; //WAS 1000//was 600
           TransferStatusOK = myDevice.BulkInEndPt.XferData(ref buf, ref len);
            if (TransferStatusOK)
            {
               StringBuilder sb = new StringBuilder(len);
               StringBuilder strData = new StringBuilder((len * 3) / 4);
               rightData = true;

              // after that data processing starts

 

 

2) The code for EZ-USB firmware on Uvision was pretty much copy-pasted from recommendation source code (EZ-USB - FPGA interface). Here is slave.c:


 

#pragma NOIV // Do not generate interrupt vectors
//-----------------------------------------------------------------------------
// File: slave.c
// Contents: Hooks required to implement USB peripheral function.
// Code written for FX2 REVE 56-pin and above.
// This firmware is used to demonstrate FX2 Slave FIF
// operation.
// Copyright (c) 2003 Cypress Semiconductor All rights reserved
//-----------------------------------------------------------------------------
#include "fx2.h"
#include "fx2regs.h"
#include "fx2sdly.h" // SYNCDELAY macro

extern BOOL GotSUD; // Received setup data flag
extern BOOL Sleep;
extern BOOL Rwuen;
extern BOOL Selfpwr;

BYTE Configuration; // Current configuration
BYTE AlternateSetting; // Alternate settings
//static WORD xdata LED_Count = 0;
//static BYTE xdata LED_Status = 0;
BOOL done_frm_fpga = 0;

// EZUSB FX2 PORTA = slave fifo enable(s), when IFCFG[1:0]=11
//sbit PA0 = IOA ^ 0; // alt. func., INT0#
//sbit PA1 = IOA ^ 1; // alt. func., INT1#
// sbit PA2 = IOA ^ 2; // is SLOE
//sbit PA3 = IOA ^ 3; // alt. func., WU2
// sbit PA4 = IOA ^ 4; // is FIFOADR0
// sbit PA5 = IOA ^ 5; // is FIFOADR1
// sbit PA6 = IOA ^ 6; // is PKTEND
// sbit PA7 = IOA ^ 7; // is FLAGD

// EZUSB FX2 PORTC i/o... port NA for 56-pin FX2
// sbit PC0 = IOC ^ 0;
// sbit PC1 = IOC ^ 1;
// sbit PC2 = IOC ^ 2;
// sbit PC3 = IOC ^ 3;
// sbit PC4 = IOC ^ 4;
// sbit PC5 = IOC ^ 5;
// sbit PC6 = IOC ^ 6;
// sbit PC7 = IOC ^ 7;

// EZUSB FX2 PORTB = FD[7:0], when IFCFG[1:0]=11
// sbit PB0 = IOB ^ 0;
// sbit PB1 = IOB ^ 1;
// sbit PB2 = IOB ^ 2;
// sbit PB3 = IOB ^ 3;
// sbit PB4 = IOB ^ 4;
// sbit PB5 = IOB ^ 5;
// sbit PB6 = IOB ^ 6;
// sbit PB7 = IOB ^ 7;

// EZUSB FX2 PORTD = FD[15:8], when IFCFG[1:0]=11 and WORDWIDE=1
//sbit PD0 = IOD ^ 0;
//sbit PD1 = IOD ^ 1;
//sbit PD2 = IOD ^ 2;
//sbit PD3 = IOD ^ 3;
//sbit PD4 = IOD ^ 4;
//sbit PD5 = IOD ^ 5;
//sbit PD6 = IOD ^ 6;
//sbit PD7 = IOD ^ 7;

// EZUSB FX2 PORTE is not bit-addressable...

//-----------------------------------------------------------------------------
// Task Dispatcher hooks
// The following hooks are called by the task dispatcher.
//-----------------------------------------------------------------------------
//void LED_Off (BYTE LED_Mask);
//void LED_On (BYTE LED_Mask);

//-----------------------------------------------------------------------------
// Task Dispatcher hooks
// The following hooks are called by the task dispatcher.
//-----------------------------------------------------------------------------
void TD_Init( void )
{ // Called once at startup

CPUCS = 0x10; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT
SYNCDELAY;
// FIFOPINPOLAR |= 0x02;
// SYNCDELAY;

// FIFOPINPOLAR = 0x02;

// PINFLAGSAB = 0x08; // FLAGA - EP6FF
// SYNCDELAY;
// PINFLAGSCD = 0xE0; // FLAGD - EP2EF
// SYNCDELAY;


//===============================
PINFLAGSAB = 0xEA; // FlagB -> EP6FF, Flag A -> EP6 EF
SYNCDELAY;
PINFLAGSCD = 0x68; // FlagC -> EP2EF , Flag D -> EP6 PF
SYNCDELAY;
//===============================


PORTACFG |= 0x40; // was 80, I installed flag d as CHIP SELECT instead of flag
SYNCDELAY;
// IFCONFIG = 0x03; // Sync or Async
IFCONFIG = 0xE3; // june 0xEB was,
SYNCDELAY;

CPUCS |= 0x02;
SYNCDELAY;
OEA = 0x03;
SYNCDELAY;
IOA = 0x03;
SYNCDELAY;

 



// EP4 and EP8 are not used in this implementation...

EP2CFG = 0xA0; //out 512 bytes, 4x, bulk
SYNCDELAY;
EP6CFG = 0xE0; // in 512 bytes, 4x, bulk
SYNCDELAY;
EP4CFG = 0x02; //clear valid bit
SYNCDELAY;
EP8CFG = 0x02; //clear valid bit
SYNCDELAY;

SYNCDELAY;
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; // see TRM section 15.14
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x04; // reset, FIFO 4
SYNCDELAY; //
FIFORESET = 0x06; // reset, FIFO 6
SYNCDELAY; //
FIFORESET = 0x08; // reset, FIFO 8
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL


// handle the case where we were already in AUTO mode...
// ...for example: back to back firmware downloads...
SYNCDELAY; //
EP2FIFOCFG = 0x00; // AUTOOUT=0, WORDWIDE=1

// core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm endp's

SYNCDELAY; //
EP2FIFOCFG = 0x11; // AUTOOUT=1, WORDWIDE=1

SYNCDELAY; //
EP6FIFOCFG = 0x0D; // AUTOIN=1, ZEROLENIN=1, WORDWIDE=1

SYNCDELAY;


}

// Code commented
//==================================================
void TD_Poll( void )
{ // Called repeatedly while the device is idle

// ...nothing to do... slave fifo's are in AUTO mode...

/* if((IOC & 0x02 ))
{;}
else
{
//IOA&=0xFD;
IOC|=0x01;
}*/

if(!(IOA & 0x08))
{
done_frm_fpga = 1;
}

if ((done_frm_fpga) && (IOA & 0x08))
{
IFCONFIG = 0x13; //FEB: changed from 03 2) changed fgrom 13 3) changed from 1B (didnt work), 4)EB
SYNCDELAY;
IOA&=0xFE; //output 0 on PA.1...SYNC signal is LOW
SYNCDELAY;
done_frm_fpga = 0;
}
if(EP68FIFOFLGS & 0x01) // If FIFO 6 is full..or change it to busy?
{
while(!(EP68FIFOFLGS & 0x02)) //wait until it does not become empty!
{
;
}
FIFORESET = 0x80; //nak-all
SYNCDELAY;
FIFORESET = 0x86;// Reset FIFO6
SYNCDELAY;
FIFORESET = 0x00;
EP6FIFOBUF [ 0 ] = 0x02;
EP6FIFOBUF [ 1 ] = 0x06;
EP6FIFOBUF [ 2 ] = 0x07;
EP6FIFOBUF [ 3 ] = 0x03;
SYNCDELAY;
EP6BCH = 0x00;
SYNCDELAY;
EP6BCL = 0x04;
}

}
//=============================================================

BOOL TD_Suspend( void )
{ // Called before the device goes into suspend mode
return( TRUE );
}

BOOL TD_Resume( void )
{ // Called after the device resumes
EZUSB_EXTWAKEUP();
return( TRUE );
}

//-----------------------------------------------------------------------------
// Device Request hooks
// The following hooks are called by the end point 0 device request parser.
//-----------------------------------------------------------------------------
BOOL DR_GetDescriptor( void )
{
return( TRUE );
}

BOOL DR_SetConfiguration( void )
{ // Called when a Set Configuration command is received

if( EZUSB_HIGHSPEED( ) )
{ // ...FX2 in high speed mode
EP6AUTOINLENH = 0x02;
SYNCDELAY;
EP6AUTOINLENL = 0x00;
SYNCDELAY;
}
else
{ // ...FX2 in full speed mode
EP6AUTOINLENH = 0x00;
SYNCDELAY;
EP8AUTOINLENH = 0x00; // set core AUTO commit len = 64 bytes
SYNCDELAY;
EP6AUTOINLENL = 0x40;
SYNCDELAY;
EP8AUTOINLENL = 0x40;
}

Configuration = SETUPDAT[ 2 ];
return( TRUE ); // Handled by user code
}

BOOL DR_GetConfiguration( void )
{ // Called when a Get Configuration command is received
EP0BUF[ 0 ] = Configuration;
EP0BCH = 0;
EP0BCL = 1;
return(TRUE); // Handled by user code
}

BOOL DR_SetInterface( void )
{ // Called when a Set Interface command is received
AlternateSetting = SETUPDAT[ 2 ];
return( TRUE ); // Handled by user code
}

BOOL DR_GetInterface( void )
{ // Called when a Set Interface command is received
EP0BUF[ 0 ] = AlternateSetting;
EP0BCH = 0;
EP0BCL = 1;
return( TRUE ); // Handled by user code
}

BOOL DR_GetStatus( void )
{
return( TRUE );
}

BOOL DR_ClearFeature( void )
{
return( TRUE );
}

BOOL DR_SetFeature( void )
{
return( TRUE );
}

BOOL DR_VendorCmnd( void )
{
return( TRUE );
}

//-----------------------------------------------------------------------------
// USB Interrupt Handlers
// The following functions are called by the USB interrupt jump table.
//-----------------------------------------------------------------------------

// Setup Data Available Interrupt Handler
void ISR_Sudav( void )
{
EZUSB_IRQ_CLEAR( );
USBIRQ = bmSUDAV; // Clear SUDAV IRQ
GotSUD = TRUE; // Set flag
}

// Setup Token Interrupt Handler
void ISR_Sutok( void )
{
EZUSB_IRQ_CLEAR( );
USBIRQ = bmSUTOK; // Clear SUTOK IRQ
}

void ISR_Sof( void )
{
EZUSB_IRQ_CLEAR( );
USBIRQ = bmSOF; // Clear SOF IRQ
}

void ISR_Ures( void ) interrupt 0
{
if ( EZUSB_HIGHSPEED( ) )
{
pConfigDscr = pHighSpeedConfigDscr;
pOtherConfigDscr = pFullSpeedConfigDscr;
}
else
{
pConfigDscr = pFullSpeedConfigDscr;
pOtherConfigDscr = pHighSpeedConfigDscr;
}

EZUSB_IRQ_CLEAR( );
USBIRQ = bmURES; // Clear URES IRQ
}

void ISR_Susp( void ) interrupt 0
{
Sleep = TRUE;
EZUSB_IRQ_CLEAR( );
USBIRQ = bmSUSP;
}

void ISR_Highspeed( void ) interrupt 0
{
if ( EZUSB_HIGHSPEED( ) )
{
pConfigDscr = pHighSpeedConfigDscr;
pOtherConfigDscr = pFullSpeedConfigDscr;
}
else
{
pConfigDscr = pFullSpeedConfigDscr;
pOtherConfigDscr = pHighSpeedConfigDscr;
}

EZUSB_IRQ_CLEAR( );
USBIRQ = bmHSGRANT;
}
void ISR_Ep0ack( void ) interrupt 0
{
}
void ISR_Stub( void ) interrupt 0
{
}
void ISR_Ep0in( void ) interrupt 0
{
}
void ISR_Ep0out( void ) interrupt 0
{
}
void ISR_Ep1in( void ) interrupt 0
{
}
void ISR_Ep1out( void ) interrupt 0
{
}
void ISR_Ep2inout( void ) interrupt 0
{
}
void ISR_Ep4inout( void ) interrupt 0
{
}
void ISR_Ep6inout( void ) interrupt 0
{
}
void ISR_Ep8inout( void ) interrupt 0
{
}
void ISR_Ibn( void ) interrupt 0
{
}
void ISR_Ep0pingnak( void ) interrupt 0
{
}
void ISR_Ep1pingnak( void ) interrupt 0
{
}
void ISR_Ep2pingnak( void ) interrupt 0
{
}
void ISR_Ep4pingnak( void ) interrupt 0
{
}
void ISR_Ep6pingnak( void ) interrupt 0
{
}
void ISR_Ep8pingnak( void ) interrupt 0
{
}
void ISR_Errorlimit( void ) interrupt 0
{
}
void ISR_Ep2piderror( void ) interrupt 0
{
}
void ISR_Ep4piderror( void ) interrupt 0
{
}
void ISR_Ep6piderror( void ) interrupt 0
{
}
void ISR_Ep8piderror( void ) interrupt 0
{
}
void ISR_Ep2pflag( void ) interrupt 0
{
}
void ISR_Ep4pflag( void ) interrupt 0
{
}
void ISR_Ep6pflag( void ) interrupt 0
{
}
void ISR_Ep8pflag( void ) interrupt 0
{
}
void ISR_Ep2eflag( void ) interrupt 0
{
}
void ISR_Ep4eflag( void ) interrupt 0
{
}
void ISR_Ep6eflag( void ) interrupt 0
{
}
void ISR_Ep8eflag( void ) interrupt 0
{
}
void ISR_Ep2fflag( void ) interrupt 0
{
}
void ISR_Ep4fflag( void ) interrupt 0
{
}
void ISR_Ep6fflag( void ) interrupt 0
{
}
void ISR_Ep8fflag( void ) interrupt 0
{
}
void ISR_GpifComplete( void ) interrupt 0
{
}
void ISR_GpifWaveform( void ) interrupt 0
{
}

 

 

Can somebody help me out on why I have this problem? I attach both codes of uVision and Visual Studio below.

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MallikaK_22
Moderator
Moderator

Hi,

Apologies for the delay in response.

Could you please let me know if you are using custom hardware or our DVK? If you are using custom hardware, please share the board schematics.

Regards,

Mallika

 

Mallika

View solution in original post

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