USB low-full-high speed peripherals Forum Discussions

Is there any vhdl/verilog bfm available to test an fpga implementation? 

My application interfaces a Spartan6/7 with the Slave FIFO of the fx2lp and I would like to verify my design against a simulation model of this part. A bfm simulating the DIO, SLOE FLAG/A/B/C , RDn, WRn , ifclk etc.

Thank you all in advance.

Hector.

Hej!

I´m trying to implement a CY7C68013A-56PVXCT as a CY7C68001-56PVXC.
There are mainly two things that I do not understand how to solve:
1:      Pin 43 have previously been a FIFOADR(2) input but now it´s a I/O, There is no register for this bit or “Command/Reserved ” function that it was previously used for, can the same function be indexed?

2:       Pin 40 was a ready signal output signal but now a I/O. Do we need to derive this ready signal on our own now or can one of the GPIF ready registers be used?

Mvh Alfred

I want to use cy7c68013a(56pin) to connect two CMOS sensers(100M) via DVP port and send the data down via usb2.is it possible?  expect a reply from you.

I am developing an GUI application which needs to interact with USB-Serial Bridge controller(CY7C65215-32LTXI) . So I am in need of header file and library files (.dll & .lib) for 32 bit & 64 bit system

Hi,

I am using FX2LP EVK and Microsemi FPGA to interface PC with my camera module. Doing this obviously requires UVC protocol encapsulation.

I am referring to " https://community.cypress.com/t5/Knowledge-Base-Articles/USB2-0-Camera-Interface-Using-FX2LP-and-Lattice-CrossLink-FPGA/ta-p/248972 " this example for implementing UVC in my setup.

I have tried to look for UVC packet information repeatedly but unable to find anything. Please guide how I can get this information.

Hej,

I´m wondering where the CY7C68001-56LTXC (QFN package) is on it´s life cycle, do you have any plans to stop the produktion of it anytime soon?
I have seen that you have stopped manufacturing of CY7C68001-56PVXC.

Regards, Alfred

Dear Sir or Madam,

We use your CY7C65213-32LTXI in our application. For our FMEDA analysis we need the FIT rate of the chip.
Could you please hand over this value to me.
Thank you very much.
Best regards

What profiles are accepted by the CY7C65211A in device recognition / BCD configuration? What voltages are allowed / expected on D+ and D-? 

We are testing a new product with several different AC adapters for USB charging, 2 of which work perfectly and 1 of which enters a charging suspend state. We have not until now expected to define compatible chargers, and would like to understand if that is necessary and what qualities are necessary. 

Chargers 1 & 2 configure the BCD to DCP, allowing full charging ✔️

• D- = 3.3V
• D+ = 3.3V

Charger 3 configures the BCD to suspend, preventing charging ✖️

• D- = 3.6 V
• D+ = 4.0 V

In general, the CY7C65211A  has performed well for us for UART communication and most BCD configuration for charging. We would like to understand if this issue has demonstrated we have made an error in design or configuration, or if Charger 3's data line voltage is not supported by the CY7C65211A . 

We are developing an example where device continuously stream data through an isochronous IN endpoint. Now my question was as interrupt and isochronous have lot of similarities :

1. Max 1024 packets in USB HS
2. both are for bandwidth guarantee.
3. Host can poll device every micro frame.

can I use my host interrupt endpoint to configure is to read from device's isochronous endpoints ?

device isochronous endpoints is following :

===>Endpoint Descriptor<===
bLength: 0x07
bDescriptorType: 0x05
bEndpointAddress: 0x81 -> Direction: IN - EndpointID: 1
bmAttributes: 0x05 -> Isochronous Transfer Type, Synchronization Type = Asynchronous, Usage Type = Data Endpoint
wMaxPacketSize: 0x0180 = 1 transactions per microframe, 0x180 max bytes
bInterval: 0x01

I understand there is NACK/ACK token in the interrupt endpoints , but let say if device ignores this NACK/ACK token can I still communicate with device using my interrupt endpoints ?