USB low-full-high speed peripherals Forum Discussions
I managed to get the application talking to the hardware somewhat correctly. (I have a few quirks, but I'm not chasing those right now.) We switched direction from another USB solution to a high speed device because of the frame timing. The system has very low data rates overall (most packets are only a few bytes at a time and not that frequent), but a full speed solution was not working. With the device I tested (DevaSys card), the delays in the system were 10-20 times slower than with the old ISA interface. Whe I looked at bus timing, the frames were 4ms.
I researched frame timing and found that high speed is supposed to have 125us subframes. With that kind of timing, I should be able to get the system working about the same speeds as ISA with possibly a few non-critical areas being a little slower.
In the initialization code the software does a send and recieve of one byte through a range of 256 possible addresses in the external chassis (it's looking to see what hardware is installed in the chassis). It does this in a tight for loop that has about 15 us per I/O call when using the ISA card. This is not a critical part of the program and I left it as is to compare timing between interfaces (I plan to move the polling to firmware eventually and just read all 256 bytes in one Bulk transfer, but that's phase II).
Looking at the traffic with a logic analyzer, I'm seeing per transaction timings of 3-4ms, not 125us. What could be causing the timing to be 24-32 times slower than expected? I find it interesting that the bus timing is almost identical to what I saw with the full speed device we rejected.
I am doing all I/O via control endpoint transfers at the moment. Many times I need to write a couple of bytes and then immediately read one or two. The bidirectionality of the control endpoint enables me to combine these into one USB call.
What is causing this and how to I fix it?
Bill
Show Lesshi all, i am doing some time-critical data transfer on EZ-USB FX2LP(cy68013a)
I use the isochronous mode, maxPacketSize = 1024, 1 transaction per uframe( 1/8 ms);
now i want to transfer data every ms, so i should set the xfer size = 8KB
that is the outlen = 8*1024.
If it works as i think, i should get the 8KB data in 1ms, but it costs about 5ms to do that.
and if i setup to get 1024KB data in 128ms, it costs about 132 ms.
Since what i am doing is time-critical, i have to find out the reason. Have you guys any idea about it?
Here is the code:
QueryPerformanceCounter(&lPerformanceCount_Start);
UCHAR *inContext = dlg->USBDevice->IsocInEndPt->BeginDataXfer(inData,inlen,&inOvLap);
if(!dlg->USBDevice->IsocInEndPt->WaitForXfer(&inOvLap,150))
{
AfxMessageBox("Time out!");
dlg->USBDevice->IsocInEndPt->Abort();
WaitForSingleObject(inOvLap.hEvent,INFINITE);
}
success = dlg->USBDevice->IsocInEndPt->FinishDataXfer(inData, inlen, &inOvLap,inContext,
isoPktInfos);
QueryPerformanceCounter(&lPerformanceCount_End);
Hi all, I cannot find the effective way to flush the data in the IN endpoint of Cy68013a.
I set the EP2IN: bulk mode, 512byte x 4. Everytime I want to read the incoming data, I have to read out the remain 2k byte data in the endpoint first. Is there any to flush the remain data? So I can get the data I want without reading the first 2k byte data.
Show LessI've tried to download Virtual COM port example but it won't load WinXP driver.
Device enumerates (seemingly) correctly and then prompts for driver. I've pointed to the attached INF file, but WinXP can't load the driver. It's visible in the device manager as unknown(other) device.
Did anyone tried to test it? I've checked on two PC's - the same result...
Show LessHi I am newbie and have been designing a simple DIO project with a CY7C64215 device. I have programmed on the CY3664 DVK and then migrated to the CY3664-28SSOP flex on my board with great success. However when I programmed my device (Programmer tells me it has been successfull) I do not get the USB to work. My code is not pretty and is pretty much the bulk example. Any advise on where to look would be appreciated.
Warenbald
Show LessI am using appnote AN66806, design example 1: 16 bit interface to external FIFO Auto Mode
I have CY3684 cypress dev kit for CY7C68013A (FX2) processor. I have 'lashed' an XiLinx to the FX2 to mimmic a FIFO.
Everything codewise is the same as the appnote
However I am getting too many clock pulses per 512 byte (256 - 16 bit word) transfer.
I am trying to read data out of the FIFO into the FX2 and then across USB to a PC using Cyconsole. I have sent the B3 vendor command to enable IN transfers and I get data.
The FPGA fills the FIFO which is 4k Words deep with a rolling count. When I request a 512 byte block, I get values and the fifo starts to empty but I am missing two words for every transfer. The first packet ends with say FF 00 00 01 (0x00FF, 0x0100) and the next packet starts 03 01 04 01 (0x0103, 0x0104)
What is the silly mistake I am making?
Thanks for your suggestions in advance
Show LessHi,
I'm thinking of using a bank of serial ADCs (AD1871 www.analog.com/en/analog-to-digital-converters/audio-ad-converters/ad1871/products/product.html) and connecting it to the GPIF.
The data is clocked in serially at about 24MHz with a 3 pin bus:
- enable
- data
- Clock
Initially this would work but just connecting the data to D0, reading in a whole byte into a FIFO (which would either be 0x1 or 0x0), transferring the whole byte over USB and doing the serial to parallel conversion on the host. Ugly but possible.
-Is it possible to program the GPIF to convert the data from serial to parallel? (thereby saving USB bandwidth)
-If yes, If I connected 2 banks of serial ADCs two 2 pins (e.g D0 and D8), but with the same clock and different chip enable, is it still possible? How about 8 banks ?
- If no, is there a better way of connecting this device to an FX2?
Show Lessusing the evl fx2 CY3681 board from cypress using the keil ver 3 (full version ...)
i can not program my program over 8k it shows over flow error if the code + data is too long >8k
the chip is connected to the external memory CY7C1019CV33-12VC i don't know how to define the setting in keil ver 3 how the fx2 will use that memory, and why the off-chip memory for the code is define as eprom and xdata as ram?
could help me define those setting ..
Thank
Show LessHi all,
is it possible to know if an incomptete IN bulk packet is waiting for transmission in case of slave FIFO and AUTOIN=1? And, if detected, is it possible to kwon the size of this incomplete data?
I tried to monitor EPxCS register waiting for the stable condition NPAK=1 but it always goes to zero also if an incomplete packet exists.
The manual says: "IN Endpoints: NPAK indicates the number of IN packets committed to USB (i.e., loaded
and armed for USB transfer), and thus unavailable to the firmware.". So what does it mean NPAK=0, that the incomplete packet is available?
Thanks!
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Hi,
Recently I am doing some development with the EZ-USB Controller. But the problem is my machine is equiped with Windows XP64 OS and Intel Core processor. As I cannot find the relevant driver for Windows XP64, Inter Core Processor, I cannot move on with my work.
So I want to know how can I find the driver for this specific requirement. Any help would be highly appreciated.
Tianlong
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