USB low-full-high speed peripherals Forum Discussions
Under the directory "..\Cypress Suite USB\Driver\bin",the drivers are classified as \w2k\x86, \wxp\x86, \wxp\x64, \wlh\x86, \wlh\x64, \win7\x86, \win7\x64...... The SYS files in these categories seem to be different. It is laborious to make a INF file, CAT file and then sign the driver for each category. So, is it possible to simply classify the driver as either 32-bit and 64 bit? If yes, then which two SYS files should I use for these two categories? Thanks in advance.
Show LessHi,
Updated firmware to implement interrupt driven data transfer instead of RI and TI register polling.
http://www.cypress.com/?rID=40248
-PRJI
Show LessI have a device with ezusb fx2 and I controlled the device using ezusb driver version 1.30 I moved to cyUSB driver version 3.4.7.0 but the communication with device is slower.
With old driver, with a fix hardware configuration, I am able to reach 30Mb/s of data trasfer, simply upgrading the driver to the cyUSB I only reach 15Mb/s.
I don't use the cypress library, I use directly the driver, below a detail of the code I use in both cases, obviously I cannot believe the new driver is slower than the old, so what I am doing wrong?
Thanks in advance for your support.
Alberto
#define MAX_BLT_SIZE (60*1024) BOOLEAN bResult; ULONG nBytes, totBytes = 0, lun; int np, i, resto;#ifdef NEWDRIVER // cyUSB.sys SINGLE_TRANSFER singleTransfer;#else BULK_TRANSFER_CONTROL bulkControl; bulkControl.pipeNum = 2;#endif np = length / MAX_BLT_SIZE; resto = length - np * MAX_BLT_SIZE; if( resto > 0 ) np++; for( i = 0; i < np; i++ ) { if( i == np - 1 ) lun = resto; else lun = MAX_BLT_SIZE;#ifndef NEWDRIVER // exUSB.sys V. 1.3 bResult = DeviceIoControl(handle, IOCTL_EZUSB_BULK_READ, &bulkControl, sizeof( BULK_TRANSFER_CONTROL ), buffer + i*MAX_BLT_SIZE, lun, &nBytes, NULL ); #else // cyUSB.sys version 3.4.7 memset( &singleTransfer, 0, sizeof( singleTransfer)); singleTransfer.ucEndpointAddress= 0x86; bResult= DeviceIoControl (handle, IOCTL_ADAPT_SEND_NON_EP0_DIRECT, &singleTransfer, sizeof( singleTransfer), buffer + i*MAX_BLT_SIZE, lun, &nBytes, NULL);#endif if( bResult == 0 ) break; totBytes += nBytes; if( nBytes < lun ) break; } if( bResult ) return totBytes; else { DWORD ErrorCode = GetLastError(); return -(LONG)ErrorCode; }Show Less
Hi,
Is there a limit to the number of devices which can be enumerated with CyUSB.sys?
My current setup is to have up to 18 EzUSB AN2131 devices connected to an XP or Win2003 machine using ezusb.sys.
I have rebuilt the driver to allow more than the original maximum of 8 devices to enumerate.
I wish to move to Windows 7 64 bit, thus I need to use CyUSB.sys, but I wish to know what the device limit is before I put the effort into redeveloping the software. If the limit is 8, and cannot be changed, I may have to stick with the 32 bit OS.
Thanks a lot.
Show LessHi,
I am using slave FIFO mode of FX2LP. I ma using data width bettween endpoints FIFO and FPGA as 16-bit. My init routine is as following.
void TD_Init (void)
{ // Called once at startup
REVCTL = 0x01;
SYNCDELAY;
CPUCS = 0x12; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT
//FIFOPINPOLAR |= 0x03;
PINFLAGSAB = 0xE9; // FLAGB - EP6.FULL, FLAGA - EP4.EMPTY
SYNCDELAY;
PINFLAGSCD = 0xF8; // FLAGD - EP8.FULL, FLAGC - EP2.EMPTY
SYNCDELAY;
PORTACFG |= 0x80;
IFCONFIG = 0x63; // External not-inverted clock, output enabled.
//IFCONFIG = 0x73; // External inverted clock, output enabled.
//IFCONFIG = 0xC3; // Internal 48 MHz clock, output disabled.
SYNCDELAY;
// EP4 and EP8 are not used in this implementation...
EP2CFG = 0xA2; //out 512 bytes, 2x, bulk
SYNCDELAY;
EP6CFG = 0xE2; // in 512 bytes, 2x, bulk
SYNCDELAY;
EP4CFG = 0xA2; //out 512 bytes, 2x, bulk
SYNCDELAY;
EP8CFG = 0xE2; // in 512 bytes, 2x, bulk
SYNCDELAY;
// EP1OIN for interrupts.
EP1INCFG = 0xA0; // out
SYNCDELAY;
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; // see TRM section 15.14
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x04; // reset, FIFO 4
SYNCDELAY; //
FIFORESET = 0x06; // reset, FIFO 6
SYNCDELAY; //
FIFORESET = 0x08; // reset, FIFO 8
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL
SYNCDELAY; //
// handle the case where we were already in AUTO mode...
// ...for example: back to back firmware downloads...
EP2FIFOCFG = 0x20; // OEP2=0, AUTOOUT=0, WORDWIDE=1
SYNCDELAY;
EP4FIFOCFG = 0x20; // OEP2=0, AUTOOUT=0, WORDWIDE=1
SYNCDELAY;
OUTPKTEND = 0x82;
SYNCDELAY;
OUTPKTEND = 0x82;
SYNCDELAY;
OUTPKTEND = 0x84;
SYNCDELAY;
OUTPKTEND = 0x84;
SYNCDELAY;
// core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm endp's
EP2FIFOCFG = 0x31; // OEP2=0, AUTOOUT=1, WORDWIDE=1
SYNCDELAY;
EP4FIFOCFG = 0x31; // OEP2=0, AUTOOUT=1, WORDWIDE=1
SYNCDELAY;
EP6FIFOCFG = 0x4D; // AUTOIN=1, ZEROLENIN=1, WORDWIDE=1, INFM = 1
SYNCDELAY;
EP8FIFOCFG = 0x4D; // AUTOIN=1, ZEROLENIN=1, WORDWIDE=1, INFM = 1
SYNCDELAY;
OUTPKTEND = 0x82;
SYNCDELAY;
OUTPKTEND = 0x82;
SYNCDELAY;
OUTPKTEND = 0x84;
SYNCDELAY;
OUTPKTEND = 0x84;
SYNCDELAY;
// Interrupts setup.
EXIF &= 0x7F; // Clear INT5 flag.
//EIP |= 0x08; // INT5 high priority.
EIE |= 0x08; // Enable INT5 external interrupt.
EA = 1; // Global Enable.
IE |= 0x80;
// Timer 0 setup
CKCON &= 0xF7; // Timer0 CLKOUT/12 = 48MHz / 12 = 2 MHz; Timer freq: clk/65535 = 30 Hz.
TMOD = (TMOD & 0xF0) | 0x01; // Timer0 mode: 16-bit
TCON |= 0x10; // Enable Timer0
}
I am not able to get data from endpoint 4 in FPGA. Can you please help me?
Thanks and Regards,
Sapan Shah
Show LessI am hacking code from BMM_USB_KIT-001. There does not appear to be a definition or #define for EP_PKT_SIZE anywhere in the main.c file or the Key.c file and yet that project builds just fine. When I cut and paste that code into my project, I get an error during the build that says it (EP_PKT_SIZE) is undefined.
When I define it as a uint16 (per the datasheet for the USBFS_LoadInEP(); API)(and assign 8 as the value, I can get most of the project working (actually, everything I have looked at so far)...
BUT, Would someone tell me why I had to define it?OR, tell me where I should have looked in the BMM code?
Thanks a TON!
Tim Miner (aka TDGM)
Show LessHello,
Manuel
Hi
I have fx2lp 56pins, and i willing to i2c working in slave fifo.
Is this can possible? i have to make data width 8bit in this chip.
If it's can do it, could you please let me know example source code like bulkloop or slavefifo ?
Show LessHi,
I'm a USB newbie and try to do something useful with the 100 pin CY7C68013A on an old FPGA dev board. While following the example for the bulk loop program on linux (AN73609), the program complains about too many endpoints. Is the example not applicable to my device or did I catch the wrong firmware?
Thanks,
Felix
Enter the choice [e.g 3] :1
----------------------------------------------------------------------------------------
Number of interfaces 1
Number of alternate settings 1
interface Number 0, Alternate Setting 0,Number of Endpoints 4
EP Address 2 Bulk OUT Endpoint
EP Address 4 Bulk OUT Endpoint
EP Address 86 Bulk IN Endpoint
EP Address 88 Bulk IN Endpoint
----------------------------------------------------------------------------------------
What do you want to do ?
1. Give information about the device.
2. Do the bulk transfer
3. Exit
Enter the choice [e.g 3] :2
-------------------------------------------------------------------------------------------------
This function is for testing the bulk transfers. It will write on OUT endpoint and read from IN endpoint
-------------------------------------------------------------------------------------------------
Found FX2LP bulkloop device, continuing...
to many Endpoints
If I have an FX2LP in "ports" mode (IFCONFIG[1:0] = 00), can I programmatically control the CTL1 & CTL2 pins? Or are those pins only accessible in slave-FIFO and GPIF modes?
Thanks!
Chris
Show Less