USB low-full-high speed peripherals Forum Discussions
Hi all
I design a board for spartan 6 and for connect to laptop need to full speed mode (2 layer pcb) but I can not use a full speed controller. can I use cy7c68013 in full mode(12 mb).I confuse to interface spartan 6 to cy7c68013 in full mode . I design interface in this picture.
Show Lesshi,
I have a FX2LP configured in slave fifo (with an external device that is reading data). I have endpoint 2 and 4 configured as bulk endpoint in manual mode, with buffered 2x of 512 byte length.
I would know if when 8051's FX2LP is accessing fifo data - before commit packet - is a safe practice, even if external device is reading data from slave fifo. 8051 checks fifo empty flag before accessdata, and external device checks hardware empty flag before read data from slave fifo.
What is the point of view of Cypress? Is there something to do for safety?
Best Regards
begos
Show LessHi,
Im using FX2LP with endpoint 2 and 4 configured as BULK OUT double buffered 512 byte in MANUAL mode, and EP 6 and 8 configured as IN endpoint ISOCRONOUS double buffered 521 byte. Data are sent from PC, FX2LP CPU access data and commit manually all data packets to an external device accessing data through slave FIFO.
I have a strange beahviour whn PC host is sending data to OUT endpoint:
When FX2LP receive an OUT transfer from PC, ep2inout or ep4inout interrupt is triggering - depending from ep target -, and CPU make some access to fifo data, then commit data to slave fifo. Sometimes, when I have an element in fifo and when two packets are coming closely in time (about 100 uSec) CPU read data from endpoint fifo buffer but some data are from first packet, and other data are from second packet. It seems that, while CPU extracts data from endpoint fifo, data are changing. It seems that data packets is copied in fifo buffer from USB even if I have not committed packet, and endpoint is in manual mode. Before access data I verify that fifo is not empty with EP2468STAT register and I commit data only at the end of cpu accesses.
If I examine usb traffic with LeCroy T3 advisor protocol analyzer, I see that second packets has an initial NYET, then it seems ok, and only after time it receives an ACK.
I have an external microcontroller that extracts data from slave fifo, and it receive data packets correctly, then data are correct in fifo buffer, there is only problem with CPU access.
Has anyone any idea?
Thanks,
Begos
Show LessHi
I want to use like following
LONG length = 2592// custom length
Has anyone tried using the CY7C65211A as a I2C slave in VCP mode? I want to write data to it from a PSoC4 and have it behave as if it were in UART mode (ie. transparently spew it out the VCP), but using the I2C interface instead. I can't find any information on what internal registers I should write to to make this happen? I'm assuming that given you can actually configure it this way that it is in fact possible (it may not be..)
Thanks
Anthony
Show LessHi:
I want to ask : can I create two threads for the two usb device, and the two usb devices work at the same time。
I find (Home › Cypress Developer Community › Forums )
http://www.cypress.com/forum/usb-high-speed-peripherals/multiple-usb-devices-application
A developer said : you cannot communicate with two devices at the same time using CyAPI.lib.
Now, Actually, I use two usb devices, One thread one device, another thread to another device.
when I open second usb device by USBDevice->Open(1),the first device will be closed?
in the C++ helpful doc (CyAPI.chm), When Open( ) is called, it first checks to see if the CCyUSBDevice object is already opened to one of the attached devices. If so, it calls Close( ), then proceeds.
It means that, at first I can't USBDevice->Open(0) in the first thread, and then USBDevice->Open(1) in the second thread.
Hi,
Firstly say hello to all:) I want to build one kind of USB key,it has two USB connectors, when we connect it to two PCs via USB port, this two PCs can access its data simultaneously. We want to use Cypress's West Bridge Astoria as key solution. West Bridge Astoria already have one USB port, we will use another component, FX3S for example, convert P port to USB so that it have another USB port. Because this USB key want to be used under DOS or EFI or WinPE environment, my question is: for the USB port on Astoria chip, could it be recognized under DOS or EFI as normal USB key does ? or it only can be used under Windows by corresponding SW driver support ? I like to confirm before we move forward, thanks you very much in advance!
Show Lesshey:
every big shot. recently i've got some new question with my fx2lp board(slave fifo, internal clock^-^). every single time after i download my firmware into my board, i found that there is no ifclk but hi level. Have i done something wrong? what should i do to avoid this?
thanks so much!!!!
Show LessAs suggested in one of the post here that EP1IN and EP1OUT cannot be used at the same time.
I'm confused like why TRM of FX2LP has mentioned both endpoints separately unlike EP2, EP4, EP6 & EP8 which are single ones and can be used only as either IN or OUT at a time.
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