FX2LP - Schematics verifications

[tayoc_1249536]

I am designing a circuit using FX2LP18 and I would like to check with you some questions.

1)Is there a problem with the pull-up voltage of the I2C line (SCLK, SDA) of EEPROM (U10) at + 3.3V_USB?
The power supply of FX2LP + 3.3V_USB starts up before the power supply of EEPROM + 3.3V_EEPROM.

2)After the power supply of FX2LP (U9) + 3.3V_USB is turned on, FX2LP is reset for 24.4ms, and after the reset is released, the power supply for EEPROM (U10) + 3.3V_EEPROM is turned on after the ON time of U8 + slow start ≒ 20µs later.

Is there a problem with this configuration?

In other words, the power of FX2LP is turned on first, the load switch for EEPROM is turned on when the FX2LP reset is released, and then the power of EEPROM is turned on 20 µs later.

The time from turning on the power of FX2LP (U9) + 3.3V_USB to releasing the reset of FX2LP (U9) is 24.4ms.
The time from the power supply of FX2LP (U9) + 3.3V_USB to the power supply for EEPROM (U10) + 3.3V_EEPROM is 24.42µs.

Regards.

[MallikaK_22 · Accepted solution]

Hi,

The I2C boot procedure is kicked off immediately after the reset is pulled away. May I know the purpose of using the load switch for EEPROM?

The only thing to ensure is the reset for both FX2LP and EEPROM should happen at the same time. From a hardware perspective, you can directly connect the FX2LP reset circuitry to EEPROM RESET/VCC.

Regards,

Mallika