FX2LP || CY7C68013A || EP buffer is getting stuck

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abhishekps
Level 3
Level 3
25 replies posted 25 sign-ins 10 replies posted

Hi

I am having one more problem with FX2LP while streaming video data.

Please help us to understand if while requesting data from FX2LP is there a possibility of FX2LP endpoint buffer getting stuck? Means FLAGB activity stops and no further data exchange happens.

When I was testing on EVK with the bulksrc example I found that if the EP buffer is not full and you request data from it then it will get stuck. Can the same scenario happen in webcam stream mode also? If so, then what are all the conditions in which we can get into this state? Please help to understand this.

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8 Replies
MallikaK_22
Moderator
Moderator
Moderator
50 likes received 750 replies posted 250 solutions authored

Hi,

Can you please share your source code and USB logs?

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Hi Mallika,

Please find the following. Here I tried to read FIFO data without sending any data to it.

abhishekps_0-1638160415779.png

 

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abhishekps
Level 3
Level 3
25 replies posted 25 sign-ins 10 replies posted

Hi

I am waiting for reply.

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MallikaK_22
Moderator
Moderator
Moderator
50 likes received 750 replies posted 250 solutions authored

Hi,

Apologies for the delay in my response.

Can you please share the waveforms for FLAG signals and then explain your problem? When you are not writing into the EP buffer what will the host read from it?

 

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Hi Mallika,

 

We are trying to display FPGA data on VLC, using UVC streaming with the help of FX2LP. I am attaching the source code in the attachment. Apologies as I cannot share FPGA code.

Now I have 2 different cases here. In both of these cases as soon as the configuration is done from FPGA end, FPGA will send data at every FLAGB empty(Low) status. I am attaching the waveform of FLAGB(channel 2 - Blue color) activity along with SLWR(channel 1 - Yellow color).

Case 1: All configuration is done from FPGA end and then VLC is turned ON. Not working case.

Please refer to FX2LP_video_stream_to_vlc__VLC_ON_AFTER_CONFIG_not_working.jpg in the attachment.

In this case we do all the configuration on FPGA and when FPGA is ready to send data on FLAGB activity, we turn ON the VLC for video display. Here no FLAGB activity is observed and no video is displayed.

 

Case 2: VLC is turned ON and then FPGA is configured to send data. Working case.

Please refer to FX2LP_video_stream_to_vlc__VLC_ON_BEFORE_CONFIG_working.jpg in the attachment.

In this case we turn ON the VLC for video display and then do all the configuration on FPGA. Here FLAGB activity is observed and video is displayed successfully.

 

Is there some constraint for FPGA here apart from timing constraint? We are using slave fifo mode with external clock as you might be able to see in attached code.

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Hi Mallika,

Just reminding you.

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Hi Mallika,

Were you able to checked this?

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Hi Mallika,

I did not get any update.

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