FX2LP || CY3689 DK || FLAG signals going HIGH at boot up || Issue with VLC

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abhishekps
Level 3
Level 3
25 replies posted 25 sign-ins 10 replies posted

Hi

I have observed that on boot up FlagB of FX2LP device in our application is going HIGH for sometime (approximately 288 millisecond), is that expected behavior of device?

Can we make it so that it doesn't go HIGH at boot up?

Also sometime while using our system with VLC for streaming, when we stop and start the stream again no data is visible on the display. Please suggest some of the possible issues that might have happened.

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1 Solution
MallikaK_22
Moderator
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50 likes received 750 replies posted 250 solutions authored

Hi,

Apologies for the delay in my response.

Please find my comments below:

1) In fifo_reset(), 0x82, 0x84, 0x86, 0x88 should be used instead of 0x02, 0x04, 0x06 and 0x08.

2) EPxFIFOCFG=0x00 (AUTOOUT=0)

SYNCDELAY

EPxFIFOCFG=0x11     ( AUTOOUT=1)

The core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm the endpoints. Also, only OUT endpoints need to be armed.

However, in your code snippet, you are arming EP6 which is an IN endpoint that is not appropriate.

Additionally, you are not initializing EP2 in AUTO mode.

Lastly, since you are using FIFOINPOLAR, the polarity of the flags is reversed which by default are active low. So FLAG B signal is now an active-high signal. Thus, when empty during the start, it will be high. If you omit FIFOINPOLAR, the FLAG signals will be active-low by default.

Regards,

Mallika

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6 Replies
MallikaK_22
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50 likes received 750 replies posted 250 solutions authored

Hi,

How are you booting FX2LP?

Are you using FlagB in your firmware?

Please share your firmware source if not confidential.

What is the issue with VLC?

Regards,

Mallika

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Hi Mallika

I am turn ON and OFF my system for reboot the device.

Yes I am using FlagB in my firmware.

Please find my settings below:

CPUCS = 0x12;

IFCONFIG = 0x13; 
SYNCDELAY;

EP2CFG = 0xA0;
SYNCDELAY;
EP6CFG = 0xE0;
SYNCDELAY;
EP4CFG &= 0x7F;
SYNCDELAY;
EP8CFG &= 0x7F; 
SYNCDELAY;

SYNCDELAY;
FIFORESET = 0x80; 
SYNCDELAY;
FIFORESET = 0x02; 
SYNCDELAY; 
FIFORESET = 0x04; 
SYNCDELAY; 
FIFORESET = 0x06; 
SYNCDELAY; 
FIFORESET = 0x08; 
SYNCDELAY; 
FIFORESET = 0x00; 

SYNCDELAY; 
EP6FIFOCFG = 0x00; 

SYNCDELAY; 
EP6FIFOCFG = 0x0D; 
SYNCDELAY;
FIFOPINPOLAR |= 0x03;
PINFLAGSAB = 0xE8;
SYNCDELAY;

When we are using VLC for streaming video using UVC on our device, in some conditions once FLAGB is set to HIGH, it never goes LOW again. We want to know what are the conditions on FX2LP which can trigger this behavior.

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MallikaK_22
Moderator
Moderator
Moderator
50 likes received 750 replies posted 250 solutions authored

Hi,

Apologies for the delay in my response.

Please find my comments below:

1) In fifo_reset(), 0x82, 0x84, 0x86, 0x88 should be used instead of 0x02, 0x04, 0x06 and 0x08.

2) EPxFIFOCFG=0x00 (AUTOOUT=0)

SYNCDELAY

EPxFIFOCFG=0x11     ( AUTOOUT=1)

The core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm the endpoints. Also, only OUT endpoints need to be armed.

However, in your code snippet, you are arming EP6 which is an IN endpoint that is not appropriate.

Additionally, you are not initializing EP2 in AUTO mode.

Lastly, since you are using FIFOINPOLAR, the polarity of the flags is reversed which by default are active low. So FLAG B signal is now an active-high signal. Thus, when empty during the start, it will be high. If you omit FIFOINPOLAR, the FLAG signals will be active-low by default.

Regards,

Mallika

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Hi Mallika,

I have tried below sequence, but it is not working for me. Before doing these settings it was working in some cases but now it is not working in any case.

CPUCS = 0x12; 

IFCONFIG = 0x13; 
SYNCDELAY;

EP2CFG = 0xA0; 
SYNCDELAY;
EP6CFG = 0xE0; 
SYNCDELAY;
EP4CFG &= 0x7F; 
SYNCDELAY;
EP8CFG &= 0x7F; 
SYNCDELAY;

SYNCDELAY;
FIFORESET = 0x80; 
SYNCDELAY; 
FIFORESET = 0x82; 
SYNCDELAY; 
FIFORESET = 0x84; 
SYNCDELAY; 
FIFORESET = 0x86; 
SYNCDELAY; 
FIFORESET = 0x88; 
SYNCDELAY; 
FIFORESET = 0x00; 

SYNCDELAY; 
EP6FIFOCFG = 0x00; 

SYNCDELAY; 
EP6FIFOCFG = 0x11; 
SYNCDELAY;
FIFOPINPOLAR |= 0x03;
PINFLAGSAB = 0xE8; 
SYNCDELAY;

 

Additionally, I need only EP6 with 4*512 buff size. I don't care about other EPs. Also FLAGB setting is set to active high for FULL FLAG and not for empty flag. That means it is showing FULL status initially and then coming to EMPTY status that is LOW level.

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MallikaK_22
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50 likes received 750 replies posted 250 solutions authored

Hi,

The configuration of EP6FIFOCFG is still not correct.

It is an IN endpoint, however, you are configuring it for AUTO OUT and arming it.

The correct configuration should be:

EP2FIFOCFG = 0x00;// AUTOOUT=0, WORDWIDE=1
// core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm endpoints
SYNCDELAY;
EP2FIFOCFG = 0x11;// AUTOOUT=1, WORDWIDE=1
SYNCDELAY;
EP6FIFOCFG = 0x0D;// AUTOIN=1, ZEROLENIN=1, WORDWIDE=1

SYNCDELAY;

Please check section 15.6.4 in the EZ USB TRM .

Regards,

Mallika

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Hi Mallika,

I tried below and the result is same as my original code. The problem that I have explained is still not fixed.

Please refer to this link also if you have not already done so: https://community.infineon.com/t5/USB-low-full-high-speed/FX2LP-CY7C68013A-EP-buffer-is-getting-stuc...

 

void TD_Init( void )
{
// Called once at startup
CPUCS = 0x12;

IFCONFIG = 0x13;
SYNCDELAY;

EP2CFG = 0xA0;
SYNCDELAY;
EP6CFG = 0xE0;
SYNCDELAY;
EP4CFG &= 0x7F;
SYNCDELAY;
EP8CFG &= 0x7F;
SYNCDELAY;

SYNCDELAY;
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x82;
SYNCDELAY;
FIFORESET = 0x84;
SYNCDELAY;
FIFORESET = 0x86;
SYNCDELAY;
FIFORESET = 0x88;
SYNCDELAY;
FIFORESET = 0x00;

SYNCDELAY;

EP2FIFOCFG = 0x00;// AUTOOUT=0, WORDWIDE=1
// core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm endpoints
SYNCDELAY;
EP2FIFOCFG = 0x11;// AUTOOUT=1, WORDWIDE=1
SYNCDELAY;
EP6FIFOCFG = 0x0D;// AUTOIN=1, ZEROLENIN=1, WORDWIDE=1

SYNCDELAY;
FIFOPINPOLAR |= 0x03;
PINFLAGSAB = 0xE8;
SYNCDELAY;
}

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