My company has been using an FX2LP with the same code for many years.
Recently we did a board spin(just got the prototypes). Theoretically the FX2LP is wired on the board the same as before.
The PC software is able to connect to the cypress.
The FX2LP correctly enumerates the device.
The PC successfully sends commands to the FX2LP, that are echoed over RS232 for debugging.
The FX2LP thinks it successfully sent data back to the PC, the RS232 debugging output shows function success.
The PC times out when calling m_ep8In->XferData. Using the software USBlyzer, I see no USB packets coming from the FX2LP.
1) When sending works and receiving fails, what chip connections / pins should we check first?
2) Is there a standard diagnostic to exercise Cypress / PC communication?
Please describe certain things like what is FX2LP connected to in the peripheral side? Is it is using GPIF/ Slave FIFO mmode? Is it Auto/ Manual mode? Based on these understandings, I would like to understand and confirm whether EP8 is actually getting data from the peripheral device. You would like to double check the connection of flags/ handshake signals. I believe you are seing NAKs in the USBLyzer trace for EP8 IN transfer request.
Endpoint 8 is set up with the following code:
EP8CFG = bmVALID | bmIN | bmBULK | bmDOUBLEBUF;
EP8FIFOCFG = bmZEROLENIN | bmWORDWIDE;
I am new to Cypress programming, so I am not sure if this answers all your setup questions or not. If not, where could I find that information? I have inherited this code from previous projects/developers.
No peripheral is connected to endpoint 8. My test consists of sending a command from the PC to the FX2LP. The FX2LP should send a response, which never seems to be sent.
Attached is output from USBlyzer. The PC sends 8 bytes of data but never gets data back.
I found the problem. At some point in initialization the IFCONFIG was getting set to use an external FPGA clock. This was present on our previous board. Using the onboard clock, USB communication works.