Hello.
I am developing a product using the CY7C68013A-56 chip.
I am working on connecting the Altera FPGA chip to the CY7C68013 chip and
sending the data to the PC.
I set the Slave FIFO mode by referring to the Cypress AN61345 example and
created the 8051 firmware.
Driver installation and loading, basic operation is completed.
However, when data is written to the FIFO by setting the slwr signal to Low
level in the FPGA The driver resets and does not load normally.
If you delete the part that makes the slwr signal low level, the USB driver
normally It works.
The problem that the USB driver is reset when the slwr signal is set
to low level has not been solved.
Thank you.
