USB EZ-PD™ Type-C Forum Discussions

Hello,

I am interesting in evaluating the CYPD3120 in a DisplayPort application.I've noticed there is a reference design called "EZ-PD™ CCG3 USB-C to DisplayPort Cable Solution"
Link: https://www.infineon.com/cms/en/product/evaluation-boards/vd_usb_ccg3_displayport/#!documents

Unfortunately, the PCB is not for sale...
I was wondering if I can get the PCB Geber files in order for manufacture it by myself.
Another Question - Just making sure I understand: Is the CYPD3120 is pre-programmed in this application or should I need to upload a specific firmware in order to operate it in the above application?
Thanks!
Nir 

Hello community,

I'm using CCG3PA for my product development.It can act as only PD/QC Sink.

So to verify Qc 2.0 Sink Functionality I'm using miniprog and Bridge control utility to initiate commands over I2C and perform required actions.

I want to apply Pull-up or Pull-down on Dp/Dm lines as per QC2.0 protocol, so I've added below function in pdss_mx_hal.c and calling whenever required, also I will be calling bc_init(0); and chgb_enable(0); explicitly  before starting QC2.0 functionality :

ccg_status_t grl_chgb_apply_sink_term(uint8_t cport, grl_chgb_snk_term_t charger_term)
{
          PPDSS_REGS_T pd = gl_pdss[cport];
         switch(charger_term)
        {
          case PULL_UP_DP://0
                   pd->bch_det_0_ctrl[cport] |= PDSS_BCH_DET_0_CTRL_RDP_PU_EN;
           break;
       case PULL_UP_DM://1
                 pd->bch_det_0_ctrl[cport] |= PDSS_BCH_DET_0_CTRL_RDM_PU_EN;
          break;
         case PULL_DOWN_DP://2
               PDSS->bch_det_0_ctrl[cport] |= PDSS_BCH_DET_0_CTRL_VDP_SRC_EN;
         break;
         case PULL_DOWN_DM://3
         pd->bch_det_0_ctrl[cport] |= PDSS_BCH_DET_0_CTRL_VDM_SRC_EN;
         break;
        case REMOVE_TERMS://4
        chgb_remove_term(cport);
         break;
       case VBUS_5V://5
        /* 0.6 on D+, D- HiZ */
       PDSS->bch_det_0_ctrl[cport] |= PDSS_BCH_DET_0_CTRL_VDP_SRC_EN;
      / * Remove other terms */
       PDSS->bch_det_0_ctrl[cport] &= ~ (PDSS_BCH_DET_0_CTRL_RDP_PU_EN |
       PDSS_BCH_DET_0_CTRL_RDM_PU_EN |
       PDSS_BCH_DET_0_CTRL_VDM_SRC_EN |
        PDSS_BCH_DET_0_CTRL_IDM_SNK_EN);
         break;
}
return CCG_STAT_SUCCESS;
}

So I will be initiating commands over I2C from bridge control utility with

Case A: Power being 3.3v in utility,

Case B: Power being 5v in utility.

In case A with input power supply to ccg3pa IC being 3v3 when I apply Pull-up on Dp/Dm line I'm seeing only ~2.75v (in multi-meter)on Dp0(TP9)/Dm0(TP12) physical available pins on DVK because of which Connected QC2.0 provider is unable to change its voltages from one range to other range, which is unexpected.

In case B with input power being 5v, I'm seeing around ~4.4v on Dp0(Tp9)/Dm0(Tp12) lines because of which DUT is changing its Vbus voltage from one range to other range which is expected.

Problem statement:

-->Provider is not changing its Vbus voltage from one range to the other range as the Dp/Dm voltage ranges are out of the tolerance value of Dp/Dm line validation range by a Provider DUT to change its Vbus voltage.

Q1: Is this sequence expected as per CCG3PA design ?

Q2: If expected, Do we Anyway to make this work at 3.3v input.

Thanks and regards,

Pranay.

Hello. IFX.

I can see that Auto CCG7D supports PD3.0 in datasheet.

Customer asked whether Auto CCG7D supports PD3.1 specification.

Please check it?

Regards.

Robert.

Dears

Please help to recommend a PD protocol chip with high cost performance, which is used in charger application scenarios, only for the source side, thank you!

Discussion started in case 0668800. 

We unsuccessfully try to modify a board CY7111 to run it as a USB PD Source (i.e.: charging a phone).

The PMG1-S1 seems to go to a latch up mode (2.5V on all I/O) when VSYS (3.3V in our case) is first applied.

At contrary if VBUS is applied first, the PMG1-S1 is starting properly.

Also here are the main questions:

1) How to power VSYS from the local PSU that could be present before any phone is attached to VBUS?

2) If we use an enable pin on VSYS power what is the minimum delay needed between VBUS valid and VSYS activated?

3) Does the XRES pull up need to be tied to VSYS or VBUS (we want to be able to use CC remote flash programming when available)?

Thank you.

Hi,

When using the firmware/binary file provided by Cypress CYPD5225-96BZXI_notebook_3_4_0_2559_0_0_0_nb.hex the device CYPD5225 fails to decode an I2C transaction generated by the Intel Tiger Lake (TGL) at address 0x53.

When using the firmware/binary file provided by Cypress CYPD5225-96BZXI_notebook_tgl_3_4_0_2559_0_0_0_nb.hex the device CYPD5225 decodes I2C I2C transactions generated by the Intel Tiger Lake (TGL) at address 0x53.

My conclusion is that there is a difference between the 2 files configuring the hardware IOs of the device.

Where or how can I find the hardware pin configuration for the two files ?

ie for the pin OVP_TRIP_P1 (K5) what is the configuration in the file  CYPD5225-96BZXI_notebook_3_4_0_2559_0_0_0_nb.hex  and in the file CYPD5225-96BZXI_notebook_tgl_3_4_0_2559_0_0_0_nb.hex ?

The datasheet says that this pin can be VBUS overvoltage output indicator for Port 1 or SCB4 I2C Data or GPIO.

I need the hardware pin configuration of all the pins of the device CYPD5225 and with the two files.

Thank you for help,

Best Regards,

TD83

Hi,

With PSoc creator, i am using the Cypress code example "CYPD5225-96BZXI_notebook_tbt".
In the "pins tab" some pins of the device CYDP5225 have no configuration.

What is the configuration for the pins not defined in the "pins tab" ?
Where can i found the default configuration for all the pins ?

Thank you for help,

Best Regards,

TD83

Hi,

I am using the .HEX file found in the directory <<Install directory>>\Cypress\EZ-PD CCGx Host SDK\CCGx\Firmware\binaries\CYPD5225-96BZXI_notebook_tbt\CYPD5225-96BZXI_notebook_tgl
to configure my Power Delivery with the tool "EZ-PD Configuration Utility".
Does this file have the same pinout configuration as the "code Example ..." ==> "Device family = CCG5" ==> "CYPD5225-96BZXI_notebook_tbt" PSoC Creator Project ?

When creating a project with PSoc Creator example "CYPD5225-96BZXI_notebook_tbt" some files are not available (ie RETIMER_FORCE_PWR_EN.C, RETIMER_FORCE_PWR_EN.h, ...).
Is it possible to recompile the project with a different setting on the IO pin ?
The pin L4 (port P0[0]) named "RETIMER_FORCE_PWR_EN" is defined as a "Digital input" with a Drive mode = High impedance digital.
I want to add an internal pull-up on this pin by changing the drive mode = resistive pull-up.
Can i recompile the project without some source files ?

How can i get the missing files ?

I want to understand the role of two particular input pins: pin L4 (named RETIMER_FORCE_PWR_EN) and pin K5 (named ADP_DETECT).
In our design we have no adapter and no retimer,  this two pins L4 and K5 have been left floating on the power delivery CYPD5225.

Thank you for help,

Best Regards,

TD83

Was planning to let the CCG5/6 do some additional "SMC" type monitoring in a system, 

i.e. hook up some high-side precision sensing + ADC's (I2C + SPI), then multiplex it and stream over another UART.

but I just noted there is no DMA on the CCG's. or are there some variants that do have this?

您好：我这边有个客户想实现UFP+SOURCE的应用，不知道这个原理图上有没有什么问题，P2.2需要在协商时给出一个低电平，复位hub。客户想要使用SWD，SCLK做下载口，在这种情况下如何通过configuration utility配置UFP.