USB EZ-PD™ Type-C Forum Discussions
Hello,
Purchased CY4500 EZ-PD Protocol Analyzer from Digikey. Installed the latest software.
When I start the analyzer , it says the firmware update is required. But can't update the FW as the driver was not installed.
Can't install the driver manually either as I can't find it in any folder.
Have looked at related posts with the same problem but they are bit outdated
Show Less應用是C to DP dongle, 參考C to DP dongle reference design 線路
但是HW 有些差異
VSYS目前是floating.
板子上有外接一個LDO - VBUS_5V to 3.3V 供給 VDDIO
再實際使用上PD 溝通上不是很穩定, 會有soft reset 現象
1. VSYS flaoting的情況下, FW or HW 需要做什麼設定?
2. VSYS不接的情況下會有什麼風險
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Hi,
I would like to find out about EPR support for dual port host controllers. Looking at the roadmap posted elsewhere on the forum, there is CCG6DF and CCG8D.
Our main supplier AVL only notes support for CCG6, however the datasheet only states CCG6 does not support EPR. Is it possible to add EPR support to the CCG6DF firmware? Or pass EPR messages through the CCG6 to the embedded controller using the host command interface to support EPR?
This would require that we add external protection circuits to the CCG6 cc pins and source path.
As an alternative does the CCG8D support EPR? And what maximum voltage can it support? we are targeting 36V.
We have a current project using the CCG6 CYPD6227, and we found during usb compliance testing with the lab that during 3A source + Vconn load test that the Vbus output voltage on the connector will drop below the usb specification of 4.75V, causing us to fail the electrical requirements for USB.
Our design powers VBUS_P_Px from a regulator operating at a minimum voltage of 5.1V. Going through a 0.005ohm current sense resistor.
Between the CCG6 and the connector we also have an EMI ferrite bead rated for 5A with 20mOhm resistance.
We measure the voltage drop across each part, and we find the large voltage drop is from the PD controller.
Do you have any plans to improve the performance in a future update to CCG6, or improve this on the CCG8 parts?
As an alternate solution, is it possible to support control of an external fet using this part to control the source power path?
I have a weird issue with a design using the CYPD6125. The board uses a PTN3460 as the DispalyPort to LVDS driver. It all works but it always takes ~1:45 (about 1 min 45 seconds) for the PD packet showing HPD high to be generated. Once that packet comes through the computer computer can connect to the PTN3460 and the LCD screen works fine (ie, the host computer sees it as a 2nd monitor).
From the PD capture you can see 56 PD packets comes through as expected setting up the DP alt mode. At this point HPD is high. After about 1 min 45 seconds packets 57 and 58 happen, then everything works. There is no change in state for HPD, it was always high. Making HPD go low (holding PTN in reset) does not cause a PD HPD packet showing low. I leaning towards a CCG software/firmware/config issue.
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I'm trying to connect to a CCG6 device (CYPD6125) with PSoC Programmer and MiniProg4 and I'm getting a "Can't Open CMSIS-DAP port" error message. This is a older project but last time I connected just fine. Nothing has been done in about 1 year, no changes to software or board. I'm guessing a Windows update has broken something. How did I fix this?
Show LessThe CCG3 is able to operate from two possible external supply sources VBUS or VSYS.
We refer to all of related reference dongle designs ( ex C to DP , C to HDMI) , the Vsys pin connect to VCONN and VBUS pin connect to VBUS.
We have a question :
1. Can we leave CCG3's Vsys pin unconnected ( floating)?
2. What is consideration the reference design want to connect VCONN to Vsys pin?
Becuase CCG3 is able to operate from supply source VBUS.
Hi all!
I would like to power my CYPD3120 chip in a different way from the datasheet and would like to know:
a. if this is possible or are there any HW changes to make in my schematic
b. What changes to do in the EZ-PD power configuration.
In the attached file you can see what are the basics of what i want to do in my design.
The target of my schematic is to *not* use VCONN from the Type-c connector - what are my options? SW changes in EZ-PD? connecting VSYS to VCONN on the chip? what about VBUS on the chip?
Thanks in advance,
Ido
Show LessHello
Q1) I understand that BCR supports clock stretch, but is the attached measurement result = 228.86us a reasonable value?
(Reading the register "BUS_VOLTAGE 0x100D")
Q2) How is the clock stretch time defined? Please explain including the relationship with Q1
Best Regards
Show LessHi cypress,
I am using CCG3PA as a sink for implementing QC 3.0 functionalities where when I use QC 4.0+ which are backward compatible it is automatically starting PD Contract. I need to stop PD contract from happening and in the same time i need Rd pull up functionalities to achieve QC 3.0 functionalities. I have used dpm_pe_stop() to stop PD protocol, as its description in the API guide says 'This function stops the policy engine, used in fault scenario where in PD protocol need to be stopped but type c manager still runs'. It didn't worked for me where i connected DUT and passes API which has this function, is there any function which will fulfill my requirement , how can I Disable PD communication and have Type c capabilities...??
Regards
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