USB EZ-PD™ Type-C

Hi 

We are building a product based on the Charge through dongle application.

I have hit a snag, we need some specific functionality on the input pdo selection. My first thought was to customize the CCG2 firmware, but not only is the example code not available, it seems the toolchain is falling out of support. (I could be wrong here)

So my question is, can I get the below behavior to work on the CCG3 while using the pre-compiled hex file for the CCG2?

- Our device dose not contain any data or display ports, so they need to be removed from the project

       +EDDIT: I have changed settings in config.h but need to use some of the controlling pins, still getting an error when reassigning them

- subtract 5W from the charge through power when separate device when activated

- when power is disconnected, the device will provide back up power, so the PDO needs to be swapped to 5V3A PDO, then stopped when battery is drained 

- no PDO higher then 12V 

Any help pointing me to the right areas would be greatly appreciated, I am relatively new to the PSOC and EZ-PD system

Thanks for your time

I am working with a CYPD6125, using the CYPD6125-40LQXI_notebook project from CCGx Host SDK as a starting point.  I am acting as the power source, and have a design that is mostly functional.  However, I've noticed some very strange behavior that is causing severe problems with my devices.  When my CYPD6125 first comes out of reset, there is a ~11 second delay between when the first device is plugged into it and when enumeration begins.

I am using a CCG EVK base board with a CY4531 CCG Daughter Card as my sink device, and providing power from my design (the DC power to the EVK is disconnected).  Using a CY4500 EZ-PD protocol analyzer, I do not see any traffic when the device is first plugged in.  11 seconds after being plugged in, I see the PD protocol traffic that I would expect to see.  I attached a logic analyzer to CC1 and CC2, and have attached the results to this post as ccg6_PD_Delay.png.

The transition from GND to 3.3V happens when I power on my design (DUT).  Two seconds later, I plug in the EVK and see the CC1 line transition to 1.5V and the CC2 line go to ground.  After the EVK is plugged in, I see CC2 going up to 5V, which I believe is my design using CC2 to act as VCONN while CC1 acts as CC.  However, 2 mS later CC1 goes down to 0.5 V, then starts to drain down to GND while CC2 is deasserted (ccg6_PD_Delay_badPulse.png).  This pattern repeats 11 times, once per second, at which time I see CC2 staying high for 70 mS, at which time PD negotiation messages being (ccg6_PD_Delay_goodPulse.png)

I only see this behavior the first time a device is connected after my DUT comes out of reset, and only when my DUT is providing power.  I see the same behavior when attaching any USB C device that does not have its own power source.  If I plug in the DC power to the EVK, PD negotiation occurs immediately after the cable is plugged in.  If I plug the EVK in with no DC power and wait the 11 seconds for it to finish PD negotiation, I can unplug it from my DUT, immediately plug it back in, and see PD negotiation begin and complete immediately (ccg6_PD_No_Delay.png).

I have copied the initialization portion of my code as main_init.c in the attached code.zip.  When using a debugger, after invoking dpm_get_info I see I see dpm_stat->attach have a value of true each time CC2 goes to 5V, then being set to false when CC2 goes back to ground.  The dpm_stat->attach variable continues to fluctuate between true and false until the 11th iteration of the CC2 line pulsing, at which point the value remains true and the connection appears stable.  I have also copied my config.h into code.zip, in case the answer lies there.

Is there an initial piece of functionality I need to perform in order to properly initialize my design?  If not, do you have any recommendations on what next steps I can take to try and determine why the PD negotiation process is taking so long to start?

Thank you in advance.

Hi,

I am reading data from the CYPD3177 for get information of the PD status. I have a few issues with the data I read over i2c in the different scenarios

1. When connector is plugged in.

Reading INTERRUPT (0x06) returns 1 -> reading DEV_RESPONSE (0x07E) returns 0x80

Type of event : Asynchronous Event generated by BCR

Response code: 0x00

Should I not expect 0x85? 0x85 requires 8 bits but the length of the Response code is only 7 bits. Please clarify

This happens twice.

2. When the adapter is turned off

Reading PD_RESPONSE (0x07E) returns 0x806412C.

Type of response is Response to a Command Register write. Should this not be Asynchronous Event generated by BCR as I have not written any command previously? (only performed reads)

The response code is 0x2C. This is not shown in the EZ-PD™ BCR Host Processor Interface Specification.

Should I not expect 0x85? 0x85 requires 8 bits but the length of the Response code is only 7 bits. Please clarify

Hi,

I am creating a PCB with CYPD3120 And would like to use display port with only 2 lanes.

I already have a discussion relating to such topic but would love other cypress engineers to help since Pranava is on vacation.

You can find our discussion here:

https://community.infineon.com/t5/USB-EZ-PD-Type-C/Powering-the-CYPD3120/m-p/343123#M6662

Would realy appreciate your help using the CYPD3120 with only 2 lanes of SS.

Best regards,

Ido

I have the CCG2 Notebook SDK I'm trying to build.

However it says it cannot find the ARM MDK toolchain.

I installed ARM MDK5.37 from  https://www2.keil.com/mdk5

from the website but I'm still getting a build error cannot find armcc.exe when I point it to KEil_5. Is there some other Keil ARM files I need to install? Maybe I need a different version that's not MDK5.37?