Hi

We have a problem with the PD-negotiation on some old Lenovo laptops. The problem seems to be that after the dock have made a PR_SWAP and all is good the dock is sending a source-cap request to the laptop and the laptop doesn't ack this with GOODCRC. After som attempt the dock forces a HARDWARE reset.

So root problem is that of course that the laptop doesn't respond to the source-cap request at all, but it is a bit unclear why the dock sends a source-cap request at all after the power swap. There is no need for that at this point.

Maybe there is a setting in the CYPD4226 FW where that behaviour can be disabled?

Attached this PD-log. First instance of the problem is on line 94-100.

Cheers

Olof

for calculation output value of ADC and calculating the input divider I have to know the value of the internal reference voltage. Would be great to have this information in the description of the cyhal method.

So what is the internal reference when calling the adc init as described in the documentation...

const cyhal_adc_channel_config_t channel_config ={ .enable_averaging = false, .min_acquisition_ns = 220, .enabled = true };

thanks rgl

I am working with a CYPD6125, using the CYPD6125-40LQXI_notebook project from CCGx Host SDK as a starting point.  I am acting as the power source, and have a design that is mostly functional.  However, I've noticed some very strange behavior that is causing severe problems with my devices.  When my CYPD6125 first comes out of reset, there is a ~11 second delay between when the first device is plugged into it and when enumeration begins.

I am using a CCG EVK base board with a CY4531 CCG Daughter Card as my sink device, and providing power from my design (the DC power to the EVK is disconnected).  Using a CY4500 EZ-PD protocol analyzer, I do not see any traffic when the device is first plugged in.  11 seconds after being plugged in, I see the PD protocol traffic that I would expect to see.  I attached a logic analyzer to CC1 and CC2, and have attached the results to this post as ccg6_PD_Delay.png.

The transition from GND to 3.3V happens when I power on my design (DUT).  Two seconds later, I plug in the EVK and see the CC1 line transition to 1.5V and the CC2 line go to ground.  After the EVK is plugged in, I see CC2 going up to 5V, which I believe is my design using CC2 to act as VCONN while CC1 acts as CC.  However, 2 mS later CC1 goes down to 0.5 V, then starts to drain down to GND while CC2 is deasserted (ccg6_PD_Delay_badPulse.png).  This pattern repeats 11 times, once per second, at which time I see CC2 staying high for 70 mS, at which time PD negotiation messages being (ccg6_PD_Delay_goodPulse.png)

I only see this behavior the first time a device is connected after my DUT comes out of reset, and only when my DUT is providing power.  I see the same behavior when attaching any USB C device that does not have its own power source.  If I plug in the DC power to the EVK, PD negotiation occurs immediately after the cable is plugged in.  If I plug the EVK in with no DC power and wait the 11 seconds for it to finish PD negotiation, I can unplug it from my DUT, immediately plug it back in, and see PD negotiation begin and complete immediately (ccg6_PD_No_Delay.png).

I have copied the initialization portion of my code as main_init.c in the attached code.zip.  When using a debugger, after invoking dpm_get_info I see I see dpm_stat->attach have a value of true each time CC2 goes to 5V, then being set to false when CC2 goes back to ground.  The dpm_stat->attach variable continues to fluctuate between true and false until the 11th iteration of the CC2 line pulsing, at which point the value remains true and the connection appears stable.  I have also copied my config.h into code.zip, in case the answer lies there.

Is there an initial piece of functionality I need to perform in order to properly initialize my design?  If not, do you have any recommendations on what next steps I can take to try and determine why the PD negotiation process is taking so long to start?

Thank you in advance.

Hi,

I am reading data from the CYPD3177 for get information of the PD status. I have a few issues with the data I read over i2c in the different scenarios

1. When connector is plugged in.

Reading INTERRUPT (0x06) returns 1 -> reading DEV_RESPONSE (0x07E) returns 0x80

Type of event : Asynchronous Event generated by BCR

Response code: 0x00

Should I not expect 0x85? 0x85 requires 8 bits but the length of the Response code is only 7 bits. Please clarify

This happens twice.

2. When the adapter is turned off

Reading PD_RESPONSE (0x07E) returns 0x806412C.

Type of response is Response to a Command Register write. Should this not be Asynchronous Event generated by BCR as I have not written any command previously? (only performed reads)

The response code is 0x2C. This is not shown in the EZ-PD™ BCR Host Processor Interface Specification.

Should I not expect 0x85? 0x85 requires 8 bits but the length of the Response code is only 7 bits. Please clarify

Hi,

After searching the information of CCG7D on WB, most of applications are adapters. Would it be possible if CCG7D be used to build a USB power consumer?

Hi,

I am creating a PCB with CYPD3120 And would like to use display port with only 2 lanes.

I already have a discussion relating to such topic but would love other cypress engineers to help since Pranava is on vacation.

You can find our discussion here:

https://community.infineon.com/t5/USB-EZ-PD-Type-C/Powering-the-CYPD3120/m-p/343123#M6662

Would realy appreciate your help using the CYPD3120 with only 2 lanes of SS.

Best regards,

Ido

Hello,

I have an Led that controls brightness through PWM, and a button that controls PWM working, but the PWM only works at begining.

#define LED_BLINK_TIMER_ID (0xC6)
#define LED_BLINK_PERIOD   (5000)

#define LED_W_ON() \
    do { \
        PWM_1_Stop(); \
        PWM_1_WritePeriod(5000); \
        PWM_1_WriteCompare(1000); \
        PWM_1_WriteCounter(0); \
        PWM_1_Enable(); \
    }while(0)
    
#define LED_W_OFF() \
    do { \
        PWM_1_Stop(); \
    }while(0)

void led_module_init(void)
{
    PWM_1_Start();
    PWM_1_Stop();
}
static void led_blink_handle(uint8_t port, timer_id_t id)
{
    (void)port;
    (void)id;
    
    timer_stop(0, LED_BLINK_TIMER_ID);
    LED_W_OFF();
}

void btn_press_detect(void)
{
    if (btn_get_press_short())
    {
        LED_W_ON();
        timer_start(0, LED_BLINK_TIMER_ID, LED_BLINK_PERIOD, led_blink_handle);
    }
}

void app_main_loop(void)
{
    btn_press_detect();
    //CyDelay(50);
}

When I first press the button, the led blinks for about 3 seconds and then goes off. When I press the button again, the led goes off, If I add CyDelay(50) to the app_main_loop function, it will always work.

Please help to see what is going on. In addition, serial port, I2C and other GPIO resources are used in the project. Looking forward to your reply!

Hello,

I have never used PSoC Creator.  I need to slightly modify the project CYPD3125-40LQXI_notebook because the multiplexer from Parade Technologies that is used on the CCG3 evaluation kit is not recommended for new design so I have used the latest one from Parade Technologies but the address map is not the same.

What is the best way to proceed?  Is it to copy the project CYPD3125-40LQXI_notebooke in my work directory?

I would like to keep only the main project in my workspace.  What is the best way to delete all the unused files from my work directory?

Thank you

Best Regards,

Patrice

I have the CCG2 Notebook SDK I'm trying to build.

However it says it cannot find the ARM MDK toolchain.

I installed ARM MDK5.37 from  https://www2.keil.com/mdk5

from the website but I'm still getting a build error cannot find armcc.exe when I point it to KEil_5. Is there some other Keil ARM files I need to install? Maybe I need a different version that's not MDK5.37?

Hello,

I have a question regarding CCG2 APIs.

I am currently using the SDK version 3.0.2, April 10, 2017.
The stack version for CCG2 is 2.3.1 Build 306.
The stack version for CCG3 device is 3.0.2 Build 905.

EZ PD part numbers are as below.
- CCG2: CYPD2122-24LQXI
- CCG3: CYPD3125-40LQXI


There is an API to change source capability mask for CCG3.
-------------------------------------------------------------------------------------------------------------------------------
ccg_status_t dpm_update_src_cap(uint8_t port, uint8_t count, pd_do_t* pdo)
-------------------------------------------------------------------------------------------------------------------------------

Here is the comment about this API.
-------------------------------------------------------------------------------------------------------------------------------
@brief This function updates the source PDOs at runtime thereby overriding the source PDOs in the config table.
@param port Port index.
@param count Count of PDOs.
@param pdo Pointer to the PDO array.
@return CCG_STAT_SUCCESS if operation is successful, CCG_STAT_BAD_PARAM otherwise.
-------------------------------------------------------------------------------------------------------------------------------

I am looking for an equivalent API to it for CCG2 devices.
It seems that there is no information about it in the API guide.
Could anyone please let me know APIs to change source capability mask at runtime for CCG2 devices?
If there is no API to do that, could you please let me know the way to produce the same result?


Thank you.