USB EZ-PD™ Type-C Forum Discussions
Setting up this discussion so we can all share data on how this should be done as there is many ways to Skin a Cat (as they say)
With specific input power we would like to provide a simple connection between multiple CCG type C SRC ports using GPIO or i2C to provide power sharing with an active current monitoring system for the input and output.
We don't want to make it as simple as the OLD TPS25740A that has factor of two capability of splitting power
This 36W system with port power management intelligently shares power between two ports providing 18Watts to Each if both are connected
Here is how we think this should be done:
Our Available input power is defined as 100watt, and we have a 4X type C output port
All CCG3/4/5/6 are sharing an i2C bus and are interconnected on the spare SCB Block
When first device is connected to any of the 4 ports it is given the maximum PDO advertisement (less overhead and less minimum capability to be a SRC, in this example we will leave 5V at 900ma available to the remaining ports)
So First Device connected will have available power at around 80-85% watts)
When another Plug event occurs on any of the other ports, a simple 5V 900ma profile is advertised and in a perfect world we would like to know how much it actually wants
so do we simply provide maximum PDO advertisement and when it requests a specific power profile and it will reset since there is not enough power but it will reset after already telling us what it actually wants...do we at this point capture the maximum power requirement save it to NVRAM for that specific CCG so we can store and compute a power profile for all devices based on how hungry they may be and prioritize accordingly ?
Now lets say the second device is a Mobile device with 28Watt request, so we Reset the primary connected device (consuming the bulk of power) and split the power availability and advertise New PDO capability, still retaining the most available amount of power to the power hungry consumer.. and keep on doing this for all subsequent connections and yes we have this working on our 2 year old design that we used ST PD IC's and dedicated MCU but it we would like to see if there is a better way to utilize what the CCG family already has built into them
How would YOU do this, anyone?
Show LessHi,
So we built a Bootloader for the CCG5 based on CCG3PA CC line bootloader as instructed by you, now it seems that the Cypress Config utility is not able to send data to program our device.
Pleases see images and let us know what other hoops we need to jump through
Not sure why
you can just see that the packets are transmitted 5 * 24 + 8 = 128 byte, not as it should be 10 * 24 + 16 = 256 byte for CCG5.
also in the configuration utility build 236, it is clear that the data packets are the same for all the rows, at the same time the build 115 send the data packets corresponding to the rows, but also cut to the size of 5 * 24 + 8.
the only thing that can be done is to prepare a cyacd file for upgrade in 128 row size, and in the bootloader to merge 2 rows to one row.
Show LessHi!
We are developing a CCG4-based dock with PS8742 mux. We have dual ports for docking and using a passive DP-mux to select which video is selected to the DP-to-HDMI converter. We are using the 3.2.1 host SDK. Updated config.h and stack_params.h included.
When connecting laptop (Dell, Macbook, HP) using the Thunderbolt-enabled ports via get 2-lane video to work. (4k2k@30Hz)
When we connected e.g. Samsung or Huawei phone or using the DP-only USB-C ports on HP / Dell laptops, the laptops thinks that there are a monitor connected, but nothing shows up on the external moniitor and it is not properbly detected. For mobiles, it gives an error message that "HDMI cable is not properly connected".
Since we don't have any USB 3/Superspeed ports, we want to always force 4-lane DP as well. Looking at the I2C communication to the PS8742 is sends 0x0030 when connecting on both Thunderbolt and non-TB ports. PD Analyzer trace included and the configuration used for CCG4.
HPD works as it should.
We are speculating that there is a problem with the number of lanes, provisioning of PS8742 and Mode C/D/E selection here maybe?
Where should we modify in configuration file and CCG4 defines to force 4-lane DP (no USB SS) or could there be some other reason why it works on Thunderbolt ports but not pure DP USB Type-C ports? I hope you can spot the errors by looking at the attached files.
Kind Regards
Olof
Show LessI am currently working on a project involving a CCG2 CYPD2122-20FNXI chip.
Other topics related to this are as follows…
Design confirmation for CCG2 CYPD2122-20FNXIT charge through USBC to USB2 adapter dongle
https://community.cypress.com/thread/36775
Programming CYPD2122-20FNXI with PSoC creator 3.3 unsupported trouble
https://community.cypress.com/thread/35051
Details on the specifics of the project are below.
I have taken the sample project (due to simplicity of removal of DP and related logic).
Simple CCG2 example firmware for power bank
This sample is very close to the final goal.
I have changed the device to the CYPD2122-20FNXI, and ported it to the PSoC Creator 4.2 development environment.
The project builds without error, and runs on the CYPD2122-20FNXI (programmed with PSoC MiniProg3), but with some issues… I will outline here.
I also have programmed the CCG2 CY4521 Evaluation Kit (includes CYPD2122-24LQXIT) with this sample project and works as intended, but porting to the CYPD2122-20FNXI results in some issues.
The FET circuit matches the CY4521 Evaluation Kit so logic can be used as-is.
Some differences, VCONN1, VCONN2 are not connected in the CYPD2122-20FNXI design.
+ While the CYPD2122-24LQXIT initially sets up as a DFP (charges the smart phone) when connected to a Samsung Galaxy S8, the CYPD2122-20FNXI sets up as a UFD. How can I setup the the CYPD2122-20FNXI to initially attempt to be a DFP (source)?
+ Attempting to issue a PD role swap via handle_pd_command(DPM_CMD_PR_SWAP, NULL, NULL); results in the PR swap taking place, accepted message, but FETs are not switched correctly… VBUS_MONITOR issue?
+ Running the project in Debug mode, disabling boot loader has issues of the CCG2 failing to respond to a VDM:DiscIdentity request from the accessory, this the accessory appears to drop the communication after repeated attempts. Failure to access data stored in .configSection perhaps?
+ I have been trying to use EZ-PD configuration software for generating the PDO table, it appears support is not available for the CYPD2122-20FNXI, I have been using the PSD table generated for the CYPD2122-24LQXIT as a result.
I have spent the last several days trying to locate these issues without much success.
The most confusing thing is what works on the CYPD2122-24LQXIT does not work on the CYPD2122-20FNXI even though the logic is identical, with exception of VCONN missing, and pins mapped differently.
Current project code and schematic are uploaded. Any insights on this would be greatly appreciated!
Below is a brief description of the current project and end goal.
The functionality that I am aiming for is a DRP accessory. This accessory is attached to a USBC based smart phone for USB2.0 data and power delivery. The power delivery can go either direction, to charge the phone from the accessory, or provide power to the accessory.
The accessory contains a battery and can be mains powered. While charging could be accomplished through the USBC connection on the accessory, this case may be rare.
The choice of the CYPD2122-20FNXI chip is due to limited space requirements and DRP functionality. A CCG3 would be more appropriate, but due to space constraints the CCG2 was chosen.
A simple schematic is uploaded, this shows connections to the CCG2. Consumer and provider control FETs are located on a separate PCB, but are marked on CCG2 pins on the schematic.
Show LessI am using a CCG3PA CYPD3174 for a 78W power adaptor. I need to be able to detect whether a 5A cable is plugged into it to allow for greater than 3A of current. I am programming with PSoc Creator. What commands do I use to read the cable ID's vbus current?
Thank you.
Show Less
I'm looking at a 100W USB PD application, derived from on the 4531 CCG3 EVK hardware.
What firmware constants, variables, or definitions should I change to allow up to 5A current output capability?
Show LessHi have a problem with a CCG3PA development kit, I have uploaded the firmware for Power Bank, but when try to recharge the battery nothing append.
I use a single cell battery 3000mAh 1C charge 2C discharge.
I moved the 0R resistance to the position for a single cell.
The device charging through type C works, while if I connect a QC3 USB power supply to the development board nothing happens.
When I connect the developer board to the PC through the micro USB cable and moving the bridges to activate the programming as per manual, often it does not detect the board but only NOTEBOOK, with an error on VDM id.
I hope you can help me
Massimo
Show LessHello everyone,
I'm trying to make a powerbank with only the USB Type C dual-role connector with CCG3PA. Anyone can tell me an alternative to the SC8915 easier to find ??
I thank you in advance
Show LessHello,
Please tell me about FW of CYPD3125-40LQXI.
Q1) Is the design of FW provided by CY4531 FW and EZ-PD CCGx Host SDK the same?
- CY4531 FW : CYPD3125-40LQXI_notebook_one/two_1_0_3_5_0_0_0_nb.cyacd
- EZ-PD CCGx Host SDK FW : CYPD3125-40LQXI_notebook_one/two_3_2_1_1658_0_0_0_nb.cyacd
As described in the release notes of EZ-PD CCGx Host SDK, I think that the version is different.
Q2) If Q1 is Yes, is the same behavior when "CYPD3125-40LQXI_notebook_one/two_3_2_1_1658_0_0_0_nb.cyacd" is programmed to CY4531?
Q3) Is CYPD3125-40LQXI programmed "CYPD3125-40LQXI_notebook_one/two_3_2_1_1658_0_0_0_nb.cyacd/hex" at the factory of Cypress?
Best regards,
Takahashi
Show Less