USB EZ-PD™ Type-C Forum Discussions
Hi!
We have a need for our dock to ask the connecting device what VID and PID they have through a Discover Identity message. Problem is that as far as we can see (and think), the connecting laptop send a "DR_Swap" directly after the 20V voltage has been negotiated and then it is the laptop sending the Discover Identity to the dock instead to initiate the alt-mode communication. See analyzer log dump.
Is there way get the dock to send a Disocver Identity before the DR-role swap? Or any other way for the dock to get VID/PID of the connecting device.
Noticed the main:sln_pd_event_handler method that is used in the CCG4 Dock ref design:
Could something be done here? Or change some PD Configuration-settings in the configuration of the FW?
Cheers
Olof
Show LessI've modified the Power SDK to work with a custom power delivery design. Our design uses an external processor acting as a master with some I2C voltage regulators attached to it. The processor continuously polls the CCG3PA (CYPD-3175) and if the CCG3PA stack requires a voltage to be delivered, it will respond to the poll with the desired voltage. This works most of the time but occasionally, I get a dropped packet or a duplicate packet.
I am using the I2C example for the CCG3PA and have tried both polling and interrupt modes. It is part of the main loop. I instrumented the packets with a sequence number and when the dpm/app tasks are not running, it works fine, i.e. packets are in sequence. When I start the DPM, it affects something in the I2C stack that causes the phenomena described above. Without any sources to the DPM, I can't tell if the dpm task call or the app call are causing some time delays that would affect the I2C. My loop is something like this:
main calls process loop
process loop pseudo code:
if (dpm_enabled)
{
dpm_task(port);
app_task(port);
}
if (I2C_1_I2C_SSTAT_WR_CMPLT)
{
respond to master request
i2c read buffer gets data
I2C_1_I2CSlaveClearWriteBuf();
(void) I2C_1_I2CSlaveClearWriteStatus();
}
if (I2C_1_I2C_SSTAT_RD_CMPLT)
{
I2C_1_I2CSlaveClearReadBuf();
(void) I2C_1_I2CSlaveClearReadStatus();
}
return to main
Does the DPM or the APP task do any blocking or anything else that might cause an occasional delay? Are there any timing tricks that I can try to help alleviate this problem?
Show LessHello i have 2 LDO with output of 3.3V for each CCG3PA should i use just one LDO for both ?
Their both on same PCB but work independently but communicate throughout I2C.
Show LessHello Cypress Community and RajathB_01,
How to initiate APDO request using CCG3PA.
And As per PD Specification we need to continuously initiate request packet for every 15 Sec.
So once after initiating APDO request and successful AMS sequence, Is above sequence handled in CCG3PA FW or Do we need to handle it explicitly by initiating APDO for every 15Sec?
For reference I've attached the Screenshot.
Regards,
Pranay.
Show LessHI RajathB_01/Cypress Community,
I am trying to test BC1.2 features of CCG3PA.
As per my requirement, I want to use CCG3PA as a Snk device and thereby test features of a connected Provider(DCP/SDP/CDP).
When I connected a provider to CCG3PA, its BC1.2 FSM is staying in OFF state (BC_FSM_OFF).
So Do CCG3PA act as BC1.2 Snk and will it be able test any BC1.2 supported Provider connected to TypeC port?
if so Do we need to enable any Enum in Firmware ?
Do we have any documents regarding this?
Thanks and Regards,
Pranay.
Show LessDoes CY4500 EZ-PD™ Protocol Analyzer support PD 3.0? When do you plan to support it?
Hi,
We are using CYPD3120 to implement HDMI over type C, in our design and needed clarifications on the below points.
1. We are supporting source function on USB type C and not sink(However, both host and device functionality is required) and not looking for battery charger function and hence, we have left VBUS pin of CYPD3120 floating. Is this fine ?
2. My understanding is , when HDMI sink is connected to the Type C connector(via type C to HDMI cable), CC pin detects it and the information can be carried to Application processor(HDMI source) and Super speed MUX via HPD of CYPD3120. Is my understanding correct?
3. We haven't planned to provide SWD connector, as I understand we can configure the CYPD3120 over I2C. Any comments?
I have attached the schematics pdf for your reference. Kindly let me know any points of concern in the schematics.
Thanks and regards,
Abhilash G
Show LessWe have a design, tightly based on reference design "39W Dual Port Car Charger" https://www.cypress.com/documentation/reference-designs/ez-pd-ccg3pa-usb-c-pps-39w-dual-port-car-charger-power-adapter
We need the source code project; the SDK project CYPD3171-24LQXQ_cla is missing the control interfaces for both Active Semi dc/dc converters.
Can one of the Cypress guys provide me this project.
Thanks in advance.
Wim
Show Less