USB EZ-PD™ Type-C Forum Discussions
We are unable to disable Source only option in Config.h
Please help, using this Southchip Reference Code , this was a port over from a 3175 project that we want to use in a DRP port on our USB HUB but we noticed that polarity control does not work at all when sinking to this port using this code since its source only
please let us know how to enable sink option as well as src option
Show LessHi. Cypress
whether do we have the ref. design in single port type-C with intel whiskey lake 8650U chipset? the customer use EC is ITE IT5570,intel whiskey lake 8650U,graphics card is NV MX250. they only need support single typ-C port with USB and DP and power source default is 5V 3A , would you advise use CCG3(CYPD3125-40LQXI), CCG4(CYPD4126-40LQXI) ,or CCG4M(CYPD4155-96BZXI)? pls give some advice on it?
thanks
flancefang
Show LessI use CCG4236 and send HPD signals via Splitter IC (SPT4320).
When the Splitter sends the HPD signal, the HPD pin of CCG4236 receives the data and converts it into a cc packet. From the picture, it can be seen that the Splitter sends 18 high low pulses, but the PD IC only sends 17 high pulses through the cc.
- 1. How do I know how long it takes between HPD pin detection and cc to send HPD_IRQ from the SDK?
- 2. Why CCG4236 only sent HPD_IRQ low and did not send HPD_IRQ high
- 3. low level width is about 1ms
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Hello,
I want to know which FW is programmed into this device (CYPD4155-96BZXI) when it is shipped from the Cypress factory.
What FW is programmed at the Cypress factory?
Best regards,
Kenji Takahashi
Show LessI have a CY4532 development kit and had a question on how current limiting is handled. I can see for the type-C port the CYPD4126 monitors and controls the current for the type-C port. My question is for the type-A port, is current limiting handled strictly by the regulator for the type-A port? Our end application will use a different regulator for both ports and the integration for the type-C port seems straightforward, but I'm trying to get some clarity as to the different control options available from the CYPD4126 to the type-A regulator.
Show LessI have loaded the example pa_opto_fb firmware for the CYPD3174 CCG3PA device to use a a baseline to develop a PD controller for our power adapter project. I need to use a PWM to drive a buck-boost device to output the voltage that was negotiated in the PD contract. How do I add PWM functionality to the firmware to control the PWM input of the buck-boost and still be PD compliant for the certification process? There is a maximum time allowed between the host requesting a voltage and the host receiving the requested voltage. How do I set this up so that I meet the USBC Power Delivery requirements?
Show LessWhere can I get source code for https://www.cypress.com/documentation/reference-designs/ez-pd-ccg3pa-usb-c-pps-39w-dual-port-car-charger-power-adapter
Hex came with reference design is working fine. Need to make little changes. Hence I need source code.
Any lead is helpful. Thanks in advance.
Thanks and Regards,
Jey
Show LessThe DataSheet for the CCG4 says there are 4 ADCs (Figure 2), but each ADC can only connect to 2 global analog multiplex busses.
Does this mean only 2 of the ADCs are useful?
Or, are there really 4 global analog multiplex busses on the CCG4? If so, how do I specify which USB-PD subsystem a GPIO pin should connect to?
I'm looking at the notebook example firmware. Both VBUS_MON_P1 and VBUS_MON_P2 are connected to AMUXA. I don't understand why this isn't a conflict.
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