USB EZ-PD™ Type-C Forum Discussions

1. I've read in other discussions that a bypass capacitor should be placed across the Rsense resistor to reduce noise. Is a 100nf 50V MLCC cap good to use. Is there an optimum value to use?
2. I am using two CCG3PA-3175-24pin controllers. I would like to program both controllers using the same 6 pin header. Using an external mux one controller chip is progammed at a time. VDDD_C1, SWD_IO_PRI, SWD_CLK are active first while VDDD_C2 and SWD_IO_SEC are disconnected. Once the primary is completed VDDD_C2, SWD_IO_SEC, SWD_CLK are active and VDD_C1 and SWD_IO_PRI and disconnected. SWD_CLK is all the time running to both chips. If the chip that isn't being powered is receiving SWD_CLK will that load the clock line down or cause other issues I'm not aware. If this is ok to program this way, once programming is completed is this shared GPIO P0.1 connection between the controller chip usable.  We would like to use this shared connection as a way for the two controllers to signal a status.
3. Is it possible to email my schematic directly to someone for review?
4. Are pull-up resistors required on the I2C liines. Can they be enabled internal to the controller chip?

Where are the PSoC Creator Project Files for the various CCGx parts?

I'd like to make minor modifications to the Bootloaders on a CCGx part. I understand I can re-create a Bootloader project using  CE221653 "PSoC 4 Bootloader and Bootloadable" as reference. I'd prefer to start with the factory loaded Bootloader.

Greg

Hello All / RajathB_01​

I'm using CCG3PA DVK kit.

I want to configure ccg3pa's Snk capabilities in Runtime.

I know how to configure using configuration utility, but my requirement is different, i want to alter snk capabilities using API.

Do we have any API in ccg3pa library that I can use for this requirement.

Thanks in Advance,

Regards,

Pranay.

Hi,

I'm using a CYPD3177 and I'd like to be able to communicate with it over an I2C bus. The device datasheet doesn't have any information about register addresses, read/write permissions, or default values that would expect to find for a device that allows communication over I2C or a SPI bus. The datasheet says to ask Cypress Technical support for further documention.

Where would I find the documentation to talk to the CYPD3177 over I2C?

Thank you for the help!

-James

Regarding KBA219845 @ https://community.cypress.com/docs/DOC-13701

I tried to work through KBA219845 and ran into questions with step 5.

Step 5 appears to be setting the project to align with the correct bootloader. Since a project doesn’t exist for a CCG4M part, this KBA has the user start with a similar CCG4 part. My experience with bootloaders is the Bootloadable file has to match the exact Bootloader file. As such, I’m not clear why the instructions are telling me to change from a single port CCG4 (CYPD4126) to a dual port CCG4 (CYPD4226) when I’m targeting a single port CCG4M (CYPS4155).

Can someone verify the procedure in step 5 and add some explanation??

If the instructions are correct, I’m not clear on how to find the Bootloader for the CYPD4226 when I’ve only loaded a project for CYPD4126. Was I supposed to load all projects?

P.S. I don’t see an option to reply or comment on the KBA at the website. Should there be an option for comment? I only found an option for feedback that lets me click on an emotion emoji.

Greg

Hello

After confirming the VCONN request, in case of 3A or more, VCONN needs 1W capacity to supply power to e-Maker.

Q1) When connecting a cable with eMaker at 3A or less, is it correct to understand that PD charging is not possible without the capacity of 1W?

Q2)  In this Q1) case, is it correct to understand that the cable with eMaker can be used by supplying power with an external LDO?

Best Regards,

Arai

When I set the voltage dividers for Isnk COarse/Fine, am I setting the maximum current allowed through the power path or is this the minimum?  I have a CYPD4533 evaluation kit and I have modified the Isnk dividers with 5k/2.4k Ohm resistors to give 2A Coarse and 500mA Fine, yet I am able to pull currents both above and below this level depending on my load.  Am I misunderstanding what is being set with these dividers, I thought this set the maximum current load through the power path?

Hi, question here.

As far as I understand, the PPS required 50mA current steps.

But in datasheet, the resolution of the current sensing amplifier is specified as 100mA.

Then How do I suppose to achieve PPS using this chip?

Are there any offerings from Cypress for a USB3.0 to DisplayPort conversion with the following details:

1. Host computer does not support DisplayPort Mode but has USB3 ports available

2. Windows 10

3. This conversion scheme/circuit shows up as a Virtual COM port in Windows 10 (we don't want to have another Monitor show up, rather we want to send bytes of display data from the USB port, through this magical bridge solution, to a physical monitor

4. Throughput of about 30 frames per second of 1080p

5. Could live with HDMI as the output if the above could be satisfied

I see that the CCGx family performs similar conversions (USB to DP/HDMI/etc.) but not sure if I can get any of them to show up as a COM port and not a separate Monitor in the Windows 10 environment.

Any help would be appreciated, thanks.

We are looking to design a dual USB-C single USB-A charging port. Using a non-isolated buck converter to provide VBUS power. The spec. sheets figure 8 is what we've settled on as a reference we want to use. Clarifications I need from you are.

1. Figure 8 doesn't show the USB-A port. Would it be correct to connect it to

5 – DP1/P1.2 USB D+/Port 1 pin 2: GPIO/UART_1_TX1/AFC/QC/BC 1.2/Apple Charging/No IEC

6 – DM1/P1.3 USB D-/Port 1 pin 3: GPIO/UART_1_RX1/AFC/QC/BC 1.2/Apple Charging/No IEC

1. As see in figure 8 for the USB-C connector current monitoring is done using a sensor resistor connector to pin 19. We would want to monitor current through the USB-A.         Would the correct approach be to connect an equvialent analog voltage to one of the GPIOs we will have available ( 5,6) configured in sofware as an analog inputs.
2. What are the max and min voltage levels of of the FB pin from the CYPD3175? Figure 8 shows it connected directly to the resistor divider connected to the converter. on past designs i have usally had to  use a buffer type device (diode, opamp) separating the CYPD3175 FB pin from converter FB pin. Is figure 8 correct in that i should connect converter FB pin to the CYPD3175 FB pin?
3. What are the steps required to have Cypress to review out schematic design?