USB EZ-PD™ Type-C

Hello,

I am interesting in evaluating the CYPD3120 in a DisplayPort application.I've noticed there is a reference design called "EZ-PD™ CCG3 USB-C to DisplayPort Cable Solution"
Link: https://www.infineon.com/cms/en/product/evaluation-boards/vd_usb_ccg3_displayport/#!documents

Unfortunately, the PCB is not for sale...
I was wondering if I can get the PCB Geber files in order for manufacture it by myself.
Another Question - Just making sure I understand: Is the CYPD3120 is pre-programmed in this application or should I need to upload a specific firmware in order to operate it in the above application?
Thanks!
Nir 

Hello community,

I'm using CCG3PA for my product development.It can act as only PD/QC Sink.

So to verify Qc 2.0 Sink Functionality I'm using miniprog and Bridge control utility to initiate commands over I2C and perform required actions.

I want to apply Pull-up or Pull-down on Dp/Dm lines as per QC2.0 protocol, so I've added below function in pdss_mx_hal.c and calling whenever required, also I will be calling bc_init(0); and chgb_enable(0); explicitly  before starting QC2.0 functionality :

ccg_status_t grl_chgb_apply_sink_term(uint8_t cport, grl_chgb_snk_term_t charger_term)
{
          PPDSS_REGS_T pd = gl_pdss[cport];
         switch(charger_term)
        {
          case PULL_UP_DP://0
                   pd->bch_det_0_ctrl[cport] |= PDSS_BCH_DET_0_CTRL_RDP_PU_EN;
           break;
       case PULL_UP_DM://1
                 pd->bch_det_0_ctrl[cport] |= PDSS_BCH_DET_0_CTRL_RDM_PU_EN;
          break;
         case PULL_DOWN_DP://2
               PDSS->bch_det_0_ctrl[cport] |= PDSS_BCH_DET_0_CTRL_VDP_SRC_EN;
         break;
         case PULL_DOWN_DM://3
         pd->bch_det_0_ctrl[cport] |= PDSS_BCH_DET_0_CTRL_VDM_SRC_EN;
         break;
        case REMOVE_TERMS://4
        chgb_remove_term(cport);
         break;
       case VBUS_5V://5
        /* 0.6 on D+, D- HiZ */
       PDSS->bch_det_0_ctrl[cport] |= PDSS_BCH_DET_0_CTRL_VDP_SRC_EN;
      / * Remove other terms */
       PDSS->bch_det_0_ctrl[cport] &= ~ (PDSS_BCH_DET_0_CTRL_RDP_PU_EN |
       PDSS_BCH_DET_0_CTRL_RDM_PU_EN |
       PDSS_BCH_DET_0_CTRL_VDM_SRC_EN |
        PDSS_BCH_DET_0_CTRL_IDM_SNK_EN);
         break;
}
return CCG_STAT_SUCCESS;
}

So I will be initiating commands over I2C from bridge control utility with

Case A: Power being 3.3v in utility,

Case B: Power being 5v in utility.

In case A with input power supply to ccg3pa IC being 3v3 when I apply Pull-up on Dp/Dm line I'm seeing only ~2.75v (in multi-meter)on Dp0(TP9)/Dm0(TP12) physical available pins on DVK because of which Connected QC2.0 provider is unable to change its voltages from one range to other range, which is unexpected.

In case B with input power being 5v, I'm seeing around ~4.4v on Dp0(Tp9)/Dm0(Tp12) lines because of which DUT is changing its Vbus voltage from one range to other range which is expected.

Problem statement:

-->Provider is not changing its Vbus voltage from one range to the other range as the Dp/Dm voltage ranges are out of the tolerance value of Dp/Dm line validation range by a Provider DUT to change its Vbus voltage.

Q1: Is this sequence expected as per CCG3PA design ?

Q2: If expected, Do we Anyway to make this work at 3.3v input.

Thanks and regards,

Pranay.

Dears

Please help to recommend a PD protocol chip with high cost performance, which is used in charger application scenarios, only for the source side, thank you!