USB EZ-PD™ Type-C Forum Discussions

I saw follow flash apis in the HOST SDK document: 1、flash_enter_mode 2、flash_access_enabled 3、flash_set_access_limits 4、flash_row_clear 5、flash_row_write 6、flash_row_read My question is can I write firmware file data of other IC into CCG5 flash? The firmware file data is used to update another MCU connected with CCG5 by I2C. If yes, how can I get the address to write the firmware file data? And where can I get byte count of a row of the CCG5 flash? Show Less

Hi, I am in the process of adding DP output functionality based on the CTD US example code provided by cypress.

Currently, in most cases, everything is working as intended, both the output and the PD nego.
However, when I reboot the tablet providing the data for the DP while viewing the DP, the DP output does not work.
Unplugging and plugging the DP cable doesn't fix it, but if I flip the type c connector between the tablet and the ccg3, the DP output becomes normal.

Do you have any idea why this is happening?
The only modification I've made to the DP is setting values to the mux after negotiation to use 2k,usb.

Additionally, could you briefly explain what happens in the ctd solution after the DP altmode command flow, if possible?

Many thanks,

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Hello,

I'm using ccg3pa,
I have to change Rp different level in usbpd 3.0, by using "typec_change_rp();" i'm able to change Rp.

-> If i'm not initiating polling data messages the rp level is whatever i configured.
-> when i initiated polling data messages that time rp will change (SinkTxOk/SinkTxNG) to avoid collision according to USBPD spec, After that messages get initiated rp will set to 3A instead of user configured rp level, is this rp value 3A is expected or not
-> If that is not expected then please let us know what i need to keep required rp level.

please refer the Capture attached

In that attached capture i configure Rp level to 1.5A after that polling data messages initiated it come back to 3A then continue with 3A.

Thanks and regards,

Kumaraswamy

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The Customer has new project and would like to use CYPD6227 to support DP/USB function,

and it is a Alder Lake N platform, and they also refer to intel reference design that uses TI PD controller that connect SOC / EC and "re-driver" by I2C bus .

 

The SDK3.5 describes about the CCG6 has three i2c bus to connect SOC, EC and "Intel Retimers".
We has question for this new project, Can we replace Intel Retimers with Re-driver  by I2C?

Which i2c pin do you suggest? 

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Customer has new  project using Alder Lake-N

the Alder Lake "N" is a intel ATOM platform 

Which PD contoller do you suggest for this Alder Lake N platform?

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Does Host - SDK 3.6 support Arrow lake and Lunar lake ?

Which PD controller is used for Arrow lake and Lunar lake platform ?

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