Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

USB EZ-PD™ Type-C Forum Discussions

Geromino
Level 5
50 replies posted 25 replies posted 10 replies posted
Level 5

Hi am  looking for  any example in Power SDK or Host SDK  of implemnet  I2C  SCB  block  as   I2C  slave   usage byte level APIs

all examples  which  i found or  community support refer me to is master  

could  you please  refere me to slave i2c scb block in  usage byte level APIs   it  will  help me  reduce  size of  my application

0 Likes
1 Solution
Sananya_14
Moderator
Moderator 750 replies posted 500 replies posted 250 solutions authored
Moderator

Hi,

Currently, we dont have such an example and to access the data as I2C slave byte by byte, you will have to implement a custom ISR that would detect the bus events properly and do a read from FIFO or write to FIFO based on bus direction. You could refer to the I2C_INT.c file and implementation in the I2C interrupt for the SCB under Generated Source for reference.

Best Regards,

Sananya

View solution in original post

0 Likes
4 Replies
Sananya_14
Moderator
Moderator 750 replies posted 500 replies posted 250 solutions authored
Moderator

Hi,

Please refer to the HPI_IF component in the CYPD3125-40LQXI_notebook project in the Host SDK for I2C slave SCB component. The SCB APIs are not directly used in the project so you could refer to the code example https://www.cypress.com/documentation/code-examples/ce224599-psoc-4-i2c-slave-serial-communication-b... to check the APIs that can be used with the same I2C slave SCB component.

Best Regards,
Sananya

0 Likes
Geromino
Level 5
50 replies posted 25 replies posted 10 replies posted
Level 5

Hi ,

i dont  want tu use  HAL of I2C Slave SCB  block   sach as I2CS_I2CSlaveClearReadBuf    i want use like this   alnog  with  timer  this example below is master   i  didnt  succses find like this as slave  could you provide  example ?

    uint32_t i;

    uint8_t  status = false;

   

    i2c_state = CyEnterCriticalSection();

    /* Clear the timeout flag and start a timer. */

    mux_xfer_timeout = false;

    timer_start (0, MUX_I2C_TIMER, MUX_I2C_TIMER_PERIOD, mux_xfer_timer_cb);

    /* If the bus is free, generate a Start condition. */

    if ((I2CM_I2C_STATUS_REG & I2CM_I2C_STATUS_BUS_BUSY) == 0)

    {

        /* Assume operation passed for now. */

        status = true;

        /* TX and RX FIFO have to be EMPTY. */

        I2CM_TX_FIFO_WR_REG = (uint32_t)(addr << 1); /* Put address in TX FIFO. */

        I2CM_ClearMasterInterruptSource (I2CM_INTR_MASTER_ALL);

        I2CM_I2C_MASTER_GENERATE_START;

        /* Wait for an ACK from the MUX. */

        while (!I2CM_CHECK_INTR_MASTER(I2CM_INTR_MASTER_I2C_BUS_ERROR |

                    I2CM_INTR_MASTER_I2C_ACK |

                    I2CM_INTR_MASTER_I2C_NACK |

                    I2CM_INTR_MASTER_I2C_ARB_LOST) &&

                (!mux_xfer_timeout));

        /* Transfer the remaining data out to the MUX. */

        for (i = 0; ((!mux_xfer_timeout) && (i < count)); i++)

        {

            /* Clear ACK interrupt from earlier. */

            I2CM_CLEAR_INTR_MASTER (I2CM_INTR_MASTER_I2C_ACK);

            I2CM_TX_FIFO_WR_REG = buffer;

            while (!I2CM_CHECK_INTR_MASTER(I2CM_INTR_MASTER_I2C_BUS_ERROR|

                        I2CM_INTR_MASTER_I2C_ACK |

                        I2CM_INTR_MASTER_I2C_NACK |

                        I2CM_INTR_MASTER_I2C_ARB_LOST) &&

                    (!mux_xfer_timeout));

        }

    }

    /* Send a STOP to the slave. */

    I2CM_I2C_MASTER_GENERATE_STOP;

    while (!I2CM_CHECK_INTR_MASTER(I2CM_INTR_MASTER_I2C_STOP |

                I2CM_INTR_MASTER_I2C_ARB_LOST |

                I2CM_INTR_MASTER_I2C_BUS_ERROR) &&

            (!mux_xfer_timeout));

    /* Check the results of the address phase. */

    if (I2CM_CHECK_INTR_MASTER (I2CM_INTR_MASTER_I2C_NACK |

                I2CM_INTR_MASTER_I2C_ARB_LOST |

                I2CM_INTR_MASTER_I2C_BUS_ERROR) ||

            (mux_xfer_timeout))

    {

        /* Transaction failed. Reset the SCB block and return error. */

        I2CM_CTRL_REG &= ((uint32) ~I2CM_CTRL_ENABLED);

        I2CM_CTRL_REG |= ((uint32)  I2CM_CTRL_ENABLED);

        status = false;

    }

    timer_stop (0, MUX_I2C_TIMER);

    CyExitCriticalSection(i2c_state);

    return (status);

0 Likes
Geromino
Level 5
50 replies posted 25 replies posted 10 replies posted
Level 5

i want reduce-i2c-scb-block-usage- to byte-level

0 Likes
Sananya_14
Moderator
Moderator 750 replies posted 500 replies posted 250 solutions authored
Moderator

Hi,

Currently, we dont have such an example and to access the data as I2C slave byte by byte, you will have to implement a custom ISR that would detect the bus events properly and do a read from FIFO or write to FIFO based on bus direction. You could refer to the I2C_INT.c file and implementation in the I2C interrupt for the SCB under Generated Source for reference.

Best Regards,

Sananya

0 Likes