Clock stretch of CYPD3177-24LQXQ

[NoAr_1540581]

Hello

Q1) I understand that BCR supports clock stretch, but is the attached measurement result = 228.86us a reasonable value?
(Reading the register "BUS_VOLTAGE 0x100D")

Q2) How is the clock stretch time defined? Please explain including the relationship with Q1

Best Regards

[Pranava_YN · Accepted solution]

Hi,

Q1) The attached time period of clock stretching is reasonable and expected.

Q2) The main reason for clock stretching in BCR before sending NAK/ACK for the preamble byte (Both read and write) is that this ACK/NACK is not directly sent by the Hardware I2C block. The BCR firmware has to service this from the firmware side. If BCR is in some other part of firmware like servicing Type-C or PD related interrupt it will stretch the clock. Therefore the time of clock stretching depends on the part of firmware that is currently being executed.

Please let me know if you need any further clarifications on this.