CYPD5225 hardware configuration

[td83]

Hi,

When using the firmware/binary file provided by Cypress CYPD5225-96BZXI_notebook_3_4_0_2559_0_0_0_nb.hex the device CYPD5225 fails to decode an I2C transaction generated by the Intel Tiger Lake (TGL) at address 0x53.

When using the firmware/binary file provided by Cypress CYPD5225-96BZXI_notebook_tgl_3_4_0_2559_0_0_0_nb.hex the device CYPD5225 decodes I2C I2C transactions generated by the Intel Tiger Lake (TGL) at address 0x53.

My conclusion is that there is a difference between the 2 files configuring the hardware IOs of the device.

Where or how can I find the hardware pin configuration for the two files ?

ie for the pin OVP_TRIP_P1 (K5) what is the configuration in the file  CYPD5225-96BZXI_notebook_3_4_0_2559_0_0_0_nb.hex  and in the file CYPD5225-96BZXI_notebook_tgl_3_4_0_2559_0_0_0_nb.hex ?

The datasheet says that this pin can be VBUS overvoltage output indicator for Port 1 or SCB4 I2C Data or GPIO.

I need the hardware pin configuration of all the pins of the device CYPD5225 and with the two files.

Thank you for help,

Best Regards,

TD83

[Pablo_EG]

Hello td83

Thank you for posting on Infineon Forums.

We understand that you require a list of the pins and their functions for the specific firmwares.

For CYPD5225-96BZXI_notebook_3_4_0_2559_0_0_0_nb.hex, as this a firmware released to the public and available in PSoC Creator, the pin functions are as seen in the project's "Pins" tab:

Regarding CYPD5225-96BZXI_notebook_tgl_3_4_0_2559_0_0_0_nb.hex, this firmware is not available to the public.
Therefore, please contact whoever provided the firmware, such as your local sales/FAE.
They will be able to provide you with a list of the pins/functions.

Best regards,
Pablo

[td83]

Hello Pablo,

Thank you for your help.

IIn the "pins tab" there is not all the pins of the device.

What is the setting for the pins not defined in the "pins tab" ?

Where can i found the default setting for all the pins ?

How can I find the use made of an input pin ?

Thank you for help,

Best Regards,

TD83.

[td83]

Hello Pablo,

I am using the .HEX file found in the directory <<Install directory>>\Cypress\EZ-PD CCGx Host SDK\CCGx\Firmware\binaries\CYPD5225-96BZXI_notebook_tbt\CYPD5225-96BZXI_notebook_tgl
to configure my Power Delivery with the tool "EZ-PD Configuration Utility".
Does this file have the same pinout as the "code Example ..." ==> "Device family = CCG5" ==> "CYPD5225-96BZXI_notebook_tbt" PSoC Creator Project ?

When creating a project with PSoc Creator example "CYPD5225-96BZXI_notebook_tbt" some files are not available (ie RETIMER_FORCE_PWR_EN.C, RETIMER_FORCE_PWR_EN.h, ...).
Is it possible to recompile the project with a different setting on the IO pin ?
The pin L4 (port P0[0]) named "RETIMER_FORCE_PWR_EN" is defined as a "Digital input" with a Drive mode = High impedance digital.
I want to add an internal pull-up on this pin by changing the drive mode = resistive pull-up.
Can i recompile the project without some source files ?

How can i get the missing files ?

I want to understand the role of two particular pins: B9 (named  RETIMER_FORCE_PWR_EN) and K5 (named ADP_DETECT).
In our design we have no adapter and no retimer so this two pins have been left floating on the power delivery CYPD5225.

Thank you for help,

Best regards,

TD83

[Pablo_EG]

Hello TD86,

Thank you for your explanation.

We understand that you are using the tgl binaries to program your device and want to check its pinout by using the tbt project.

These two projects have different pinouts.
You can change the IO pin configuration to your requirement.
Just be sure to change the code accordingly if there is any conflict.

These are the pin differences:

You can recompile the project with your changes.

If you require source files that are not present in the project or any other project, please contact your local Infineon sales representative or local FAE.
They will guide you. This is because we cannot discuss confidential topics such as these source files on the forum.
I hope you can understand.

The L4 pin RETIMER_FORCE_PWR_EN is an active-high GPIO output from SoC.
This pin indicates when to enable power to the retimer.
The K5 pin ADP_DETECT is an active low input used to indicate DC barrel presence.
If these are not used, please disable them and comment out the code sections where these are referenced.

Best regards,
Pablo

[td83]

Hello Pablo,

I do not understand 2 things in your previous mail.

You said that the two files <<Install directory>>\Cypress\EZ-PD CCGx Host SDK\CCGx\Firmware\binaries\CYPD5225-96BZXI_notebook_tbt\CYPD5225-96BZXI_notebook_tgl  from "EZ-PD Configuration Utility" tool and the file found in PSoC Creator "code Example ..." ==> "Device family = CCG5" ==> "CYPD5225-96BZXI_notebook_tbt" are different.

But as i am using the .HEX file found in the directory <<Install directory>>\Cypress\EZ-PD CCGx Host SDK\CCGx\Firmware\binaries\CYPD5225-96BZXI_notebook_tbt\CYPD5225-96BZXI_notebook_tgl
to configure my Power Delivery with the tool "EZ-PD Configuration Utility", I need the pinout of this file to check if my design is right.

Where can i found the pinout associated with the .HEX file found in the directory <<Install directory>>\Cypress\EZ-PD CCGx Host SDK\CCGx\Firmware\binaries\CYPD5225-96BZXI_notebook_tbt\CYPD5225-96BZXI_notebook_tgl ?

You said "The L4 pin RETIMER_FORCE_PWR_EN is an active-high GPIO output from SoC" but

for this pin PSoc Creator is an Input see file "L4_config.PNG"

The pin L4 is it an Input or an output ?

Thank you for help,

Best Regards,

TD83.

[Pablo_EG · Accepted solution]

Hello Mielos,

I apologize if my explanation was not clear.

The TBT project is intended to use with both Tiger Lake as well as Ice Lake platforms.
The TBT project supports both platforms.
In order to use it in Tiger Lake platforms, we need to use the TGL configuration file.
By default, the TBT project does not have the TGL config.c file.
This is the difference between the TBT default binary and the TGL binary.

Therefore, TBT and TGL hex files are NOT the same.

The pinout for the TBT and TGL binary is the SAME.
"The L4 pin RETIMER_FORCE_PWR_EN is an active-high GPIO output from SoC"
This statement says that L4 is an OUTPUT from SOC, which means that it is an INPUT to CCG5.
The signal goes out from the SoC and goes into CCG5.

As per my previous post, the pins tab shows all of the pins, colored by their type.
This pinout is the same for the TBT and TGL binary.

I hope my message was clearer this time.

Best regards,
Pablo