In my application, I have the CYPD3171 powered from VBUS_IN_DISCHARGE. It generates 3.3V on VDDD from an internal regulator. The datasheet says not to use this to power external devices. However, I am using it for the pull up resistors for I2c communications. The datasheet says that GPIO cannot handle having a voltage on I2C lines when the CYPD3171 is powered down, so I figured pulling up to VDDD is ok since it is internally generated. Every 32 ms or so, the voltage on VDDD sags down from 3.3V to approximately 1.5V before rapidly shooting back up to 3.3V. If I increase the capacitance on VDDD, it still sags to 1.5V but the amount of time it takes to drop from 3.3 to 1.5 increases, which seems to suggest that there is some feedback on VDDD and the voltage is allowed to drop to 1.5V on purpose. Actually, there is a voltage spike before the drop (on the EVK as well as my board with a 1 uF and 100 nF cap installed on VDDD), but the spike goes away with a 4.7 uF capacitor added to VDDD. I started a new example project (power adapter "cla" project) for the CYPD3171 and flashed it to the CY4532 EVK. I powered the EVK from VBUS_IN on J4 (J2, J3, J4 in default position, Jumper on J6 removed, J5 and J7 removed) and saw the same exact behavior on VDDD. Enabling or disabling deep sleep has no effect on this. Is there some change I need to make to the firmware to support being powered from VBUS_IN_DISCHARGE? Thanks.
