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USB EZ-PD™ Type-C

Michael_Y
New Contributor II

Hi Abhilash_P,

I inherited a board with CYPD3125-40QXIT, built by a departed engineer who followed the Cypress reference design.  2 FETs were used, enabled by VBUS_C_CTRL1,0 (pin29, 30), which I need to default to "high".  Otherwise the board won't get power. 

--I have not purchased a CY4531 EZ-PD CCG3 Evaluation Kit, nor do I plan to buy one.  So,  I can't use EZ-PD Config Utility (which may not allow me to default these 2 pins to high anyway).

--I have MiniProg3 and setup the SWD interface to the board.  PSoC programmer was able to see the device.

--I have also installed PSoC Creator 4.3, and have been reading the user manual to try to figure out a way to program these two pins.

--So far I haven't found a way at all.  These two pins were labeled as "power" and no manual driven popups to allow modifications. One Infineon FAE suggested to insert "pd_internal_cfet_on() function after the drive mode is set".  I searched in CYPD3125-40LQXI_notebook01, and found in pdss_hal.c, line4065, pd_internal_cfet_on() is already there. 

So my questions are as follows,

1. Does the device usually shipped with CYPD3125-40LQXI_notebook01 programmed?  

2. If not, should I program the device again with CYPD3125-40LQXI_notebook01?  Any modification needed to default the 2 pins? If so, how and where to modify?

Thank you in advance.

Regards,

Michael Y

 

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1 Solution
ShifangZ_26
Moderator
Moderator

Hello Michael,

CCG3 firmware disable VBUS consumer path by default when Type-C interface is not attach any Type-C Source.

1.  N MOS FET control logic is 

ENABLE path: High

DISABLE path: LOW.

 

2. Type-C VSafe0V specification, VBUS voltage shall be <800mV.

 

3. CCG3 can be powered from VBUS with present Rd_DB. And then, enable consumer path. 

 

If you insist to enable consumer path, you could change the drive mode of VBUS_C_CTRL by assert APP_VBUS_SNK_FET_ON_P1() into the firmware code app.c or main.c, where the one you could like to. But I am not recommend to change it, since APP_VBUS_SNK_FET_ON_P1() will be called by firmware as per Type-C state machine and Power Delivery state machine, you have to filter out which case is the one you could like to enable the consumer path but Type-C state machine and Power Delivery state machine will not enable.

 

Best Regards,

Lisa

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8 Replies
ShifangZ_26
Moderator
Moderator

Hello Michael,

 

1. Does the device usually shipped with CYPD3125-40LQXI_notebook01 programmed?  

>> The CYPD3125 will be pre-programmed with  CYPD3125-40LQXI_i2c_boot_1_0_3_461_0_0_0_nb.hex . If you have been installed Ez-PD Host SDK3.4 (link:  ), you could find the binary under folder: C:\Program Files (x86)\Cypress\EZ-PD CCGx Host SDK\CCGx\Firmware\binaries\CYPD3125-40LQXI_notebook 

2. If not, should I program the device again with CYPD3125-40LQXI_notebook01?  Any modification needed to default the 2 pins? If so, how and where to modify?

>> Yes, you can programming CYPD3125 with SWD. By default, the VBUS_P_CTRL using N MOS FET control logic, if you have changed hardware from N  MOS FET to P MOS FET, you just need change the main.c file line 378

Original: pd_hal_set_fet_drive(PD_FET_DR_N_JN_FET, PD_FET_DR_N_JN_FET);

change to :  pd_hal_set_fet_drive(PD_FET_DR_P_JN_FET, PD_FET_DR_P_JN_FET);

Best Regards,

Lisa

Lisa

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Michael_Y
New Contributor II

Hi Lisa,

Thank you for the reply.  The board design uses AO4838, a dual N-channel FET, controlled by VBUS_C_CTRL (pin29 and pin30).  I just want to confirm with you, will "pd_hal_set_fet_drive(PD_FET_DR_N_JN_FET, PD_FET_DR_N_JN_FET)" also default these 2 pins high?

The comment in Main.c seems to imply that this line of code controls all N_JN_FET, although it didn't say whether the pins are defaulted high or low.

Michael_Y_0-1633710156187.png

Thanks,

Michael

 

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ShifangZ_26
Moderator
Moderator

Hello Michael,

CCG3 firmware disable VBUS consumer path by default when Type-C interface is not attach any Type-C Source.

1.  N MOS FET control logic is 

ENABLE path: High

DISABLE path: LOW.

 

2. Type-C VSafe0V specification, VBUS voltage shall be <800mV.

 

3. CCG3 can be powered from VBUS with present Rd_DB. And then, enable consumer path. 

 

If you insist to enable consumer path, you could change the drive mode of VBUS_C_CTRL by assert APP_VBUS_SNK_FET_ON_P1() into the firmware code app.c or main.c, where the one you could like to. But I am not recommend to change it, since APP_VBUS_SNK_FET_ON_P1() will be called by firmware as per Type-C state machine and Power Delivery state machine, you have to filter out which case is the one you could like to enable the consumer path but Type-C state machine and Power Delivery state machine will not enable.

 

Best Regards,

Lisa

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Michael_Y
New Contributor II

Hi Lisa,

Here is how my device works,

1. Upstream is either USB-C or DP, which will provide data but may not provide power.

2. Downstream is a USB-C that connects to a monitor, which will receive data and provide power.

So, at my device will always be a power consumer.  I don't have to worry about Power Delivery state machine.

I plan to try force VBUS_C_CTRL on.  But I couldn't find APP_VBUS_SNK_FET_ON_P1() in either app.c or main.c.  Did you mean insert this line?  If so, where should I insert it?

Thanks,

Michael 

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ShifangZ_26
Moderator
Moderator

Hello Michael,

 

APP_VBUS_SNK_FET_ON_P1() is defined in config.h. And it is called in psink.c. Since you mentioned that you could like to force to enable consumer path, you could assert APP_VBUS_SNK_FET_ON_P1() in main.c before while () loop. And also, you could assert it in case APP_EVT_TYPEC_STARTED: @ app.c file. 

 

Best Regards,

Lisa

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Michael_Y
New Contributor II

Hi Lisa,

I am not intimately familiar with the inter working of these codes.  Therefore I will need very clear, step by step instructions to accomplish what we set out to do, samples preferred. 

1. Does "APP_VBUS_SNK_FET_ON_P1()" control VBUS_C signals.  That is, pin29 and pin30.  Please answer yes or no.  I am sure "APP_VBUS_SNK_FET_ON_P1()" controls VBUS_P signals.

2. main.c has multiple while() loop.  Which one is it?  Could you please provide line number? what exactly to put in? If you could create a piece of sample code for me to follow, that would be great. We are talking only a few lines. 

3.  What do mean by "APP_VBUS_SNK_FET_ON_P1()"?  I only need one method to assert pin29, 30 at power up (consumer path as Cypress may refer it as). 

4.  When you said assert, do you mean putting in ON in parenthesis, such as in  APP_VBUS_SNK_FET_ON_P1(ON)?

Regards,

Michael

 

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Michael_Y
New Contributor II

Hi Lisa,

With my local FAE's help, I now understand I need to use EZ-PD Config to set up power sink, and PSoC to default the V_BUS_C pins.  So the first step,

I used EZ-PD Config to setup power sink and here is the screen shot.  Could you verify that I have done it right.  

Michael_Y_0-1634334158145.png

1) I am not sure if Port role should be set to dual or sink.

2) I am not sure if Default port role means DFP.  There is no place for me to choose UFP, or DFP.  Couldn't find that information from the manual either.

 

Thanks,

Michael

 

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