CYPD3125 Display Port Source HPD always low

[nyoung]

We are trying to get a design working with display port over USBC. We are using an adapter to attach the DP monitor and power our device. The firmware of the CCG3 is based on the Cypress notebook example. The DP HPD pin I've set to GPIO1 by defining HPD_P0_PORT_PIN and HPD_P1_PORT_PIN to be GPIO_PORT_1_PIN_1, the pin we want, in pdss_hal.h. This pin is tied to our display port controller's HPD pin. This pin is always low even with a monitor attached to the adapter. The CY4500 protocol analyzer shows DP negotiations taking place. The monitor also responds initially by coming out of standby but nothing ever displays with it eventually going back to sleep.

The implementation does not have USB2 or SBU tied to the CYPD3125. We have a separate, passive mux that handles orientation of the cable based on a CCG3 GPIO providing polarity (which does work fine). But two display port lanes are always on the USB superspeed lines and the AUX channel is always on SBU lines. CC pins are tied to the CCG3.

I'm not entirely sure where to start debugging the firmware, any help is appreciated. 

[ShifangZ_26]

Hello ,

1. Since you mentioned that you are going to debug the design. please kindly make sure:

a. The hardware schematic design and firmware is matched.

b. The CCG3 CYPD3125 is powered well and working. Checking the VCCD is 1.8V or not. 

c. After firmware programmed, please make sure CC1/CC2 of Type-C interface is toggling or assert to high(3.3V). 

2. Attach the C to DP dongle with Monitor connected. 

a. Use PD analyzer to catch the PD message of Type-C port. 

b. Make sure the DP ALT mode have been entered and HPD status have been updated in the PD negotation (Since you are looking for HPD high, please make sure HPD was high status in the PD negotation.)

c. Check firmware with UART debug if HPD status was high and GPIO of CCG3 firmware routed was not. 

Best Regards,

Lisa

[nyoung]

1.The schematic and firmware design are matched. The CCG3 does work and everything powers up ok. It negotiates power correctly and provides cable polarity correctly for our mux circuitry. One of the CC lines is held low constantly, the other toggles constantly.

2. The PD analyzer does show display port alt mode taking effect but I don't see anything in the messages about HPD going high. There is one DisplayPort Status Update message that shows HPD being low. I attached the full log from the analyzer. I see the same messages with the monitor connected to the dongle and without it.

I'm still working on getting the psoc creator debugging working.