CCG3PA: guidance for using OpenOCD and FT2232H?

[drewfustini]

I am using Cypress OpenOCD  from GitHub which is currently 4.1.  I have created a pull request which adds the silicon family ID 0xB0 for CCG3PA.

I am able to successfully program the CCG3PA with OpenOCD using psoc4.cfg and MiniProg4 on a Linux system (Ubuntu 20.04).

However, the goal here is to create a factory programming and test jig for a CCG3PA-based product.  It is not desired to embed a MiniProg4 inside of the the test jig.  We would like to use a more cost effective SWD interface like the FTDI FT2232H.

I am able to successfully program a PSoC 4200M with OpenOCD using psoc4.cfg with a FTH2232H board configured for SWD.

However, I am not able to program the CCG3PA  with that same configuration: OpenOCD using psoc4.cfg with FTH2232H board configured for SWD.

This thread is to hopefully gain any insights into why it does not work.

[drewfustini]

OpenOCD using psoc4.cfg  for CCG3PA and kitprog3.cfg for MiniProg4: OKAY

First, let me show the setup where I can successfully program the CCG3PA with OpenOCD and the MiniProg4.  I am using the main board from the CCG3PA EVK.   The MiniProg header is connected to VTarg, GND, SWCLK and SWDIO on the MiniProg4.  My Salaea logic analyzer probes are also connected to SWCLK, SWDIO and GND.  See attached photo.

I am using my pull request on Cypress OpenOCD which simply adds the family ID for CCG3PA as a PSoC4 device.  Here is the command I use to verify that OpenOCD can acquire the CCG3PA.  It uses unmodified psoc4.cfg and kitprog3.cfg.

openocd -s tcl -f interface/kitprog3.cfg -f target/psoc4.cfg -c "kitprog3 power_config on 3300; kitprog3 acquire_config on 0 1 5; init; kitprog3 acquire_psoc; init; exit"

The output:

Open On-Chip Debugger 0.10.0+dev-gd526e667dedf-dirty (2021-02-22-17:17)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "swd". To override use 'transport select <transport>'.
adapter speed: 2000 kHz
** Auto-acquire enabled, use "set PSOC4_USE_ACQUIRE 0" to disable
cortex_m reset_config sysresetreq
Info : CMSIS-DAP: SWD  Supported
Info : CMSIS-DAP: JTAG Supported
Info : CMSIS-DAP: FW Version = 2.0.0
Info : CMSIS-DAP: Interface Initialised (SWD)
Info : SWCLK/TCK = 0 SWDIO/TMS = 1 TDI = 0 TDO = 0 nTRST = 0 nRESET = 1
Info : CMSIS-DAP: Interface ready
Info : KitProg3: FW version: 2.10.878
Info : KitProg3: Pipelined transfers enabled
Info : kitprog3: powering up target device using KitProg3 (VTarg = 3300 mV)
Info : VTarget = 3.292 V
Info : kitprog3: acquiring the device...
Info : clock speed 2000 kHz
Info : SWD DPIDR 0x0bb11477
Info : psoc4.cpu: hardware has 4 breakpoints, 2 watchpoints
*****************************************
** Silicon: 0x2003, Family: 0xB0, Rev.: 0x12 (A1)
** Detected Family: CCG3PA USB Type-C Port Controller
** Detected Main Flash size, kb: 64
** Chip Protection: protection OPEN
*****************************************
Info : starting gdb server for psoc4.cpu on 3333
Info : Listening on port 3333 for gdb connections
Info : kitprog3: acquiring the device...
Info : psoc4.cpu: external reset detected
Info : psoc4.dap: powering down debug domain...

I just want to show the successful acquire of CCG3PA in the logic analyzer traces so I did not do the full programming sequence.  Those interested, I have the command to successfully program the CCG3PA and the full output from OpenOCD in another post.

I have attached a screenshot from the Salaea Logic which shows SWDIO and SWCLK.  It shows that there is Line Reset followed by request for IDCODE.  The CCG3PA responds with the IDCODE for the Cortex-M0 as expected.  See the attached screenshots.

In summary, it works as expected.

[drewfustini]

OpenOCD using psoc4.cfg  for PSoC 4200M and FT2232H adapter: OKAY

The Tigard is an interface board with the FTDI FT2232H.  It uses tigard-swd.cfg which is as follows:

adapter driver ftdi
transport select swd
ftdi_vid_pid 0x0403 0x6010
ftdi_channel 1
adapter speed 2000
ftdi_layout_init 0x0018 0x05fb
ftdi_layout_signal SWD_EN -data 0
ftdi_layout_signal nSRST -ndata 0x0020 -noe 0x0040

 I have a PSoC4 4200M (CY8C4247AZI) from the CY8CKIT-049 devkit where I broke off the KitProg programmer and instead connected the Tigard (FT2232H) to the SWD pins.  The Tigard is able to supply 3.3V on the VTarg pin.  The Salaea logic is connected to SWDIO, SWCLK and GND on the PSoC4 4200M.  See attached photo.

OpenOCD is able to program a hex file into the PSoC 4200M flash.  However, for this test, I able just going to do that init phase.  Here is the command I use:

openocd -f ~/tigard-swd.cfg -f ./tcl/target/psoc4.cfg -c " init; exit"

Here is the output as expected:

Open On-Chip Debugger 0.10.0+dev-gd526e667d-dirty (2021-02-10-23:02)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
Info : FTDI SWD mode enabled
adapter speed: 1000 kHz
adapter speed: 2000 kHz
** Test Mode acquire not supported by selected adapter
cortex_m reset_config sysresetreq
START WITH CONFIGURE
START WITH flash bank
START WITH add_verify_range
Info : clock speed 2000 kHz
Info : SWD DPIDR 0x0bb11477
Info : psoc4.cpu: hardware has 4 breakpoints, 2 watchpoints
*****************************************
** Silicon: 0x112D, Family: 0xA1, Rev.: 0x13 (A2)
** Detected Family: PSoC 4100M/4200M
** Detected Main Flash size, kb: 128
** Chip Protection: protection OPEN
*****************************************
Info : starting gdb server for psoc4.cpu on 3333
Info : Listening on port 3333 for gdb connections
Info : psoc4.dap: powering down debug domain...

The logic analyzer shows that:

• Line reset
• Request DebugPort Read IDCODE to the target
• WData 0x0BB11477 reg IDCODE response from the target which confirms it is a Cortex M0 
  • Cortex-M0 is DAP DP ID 0x0BB11477

 See the attached screenshots.

In summary, it works as expected.

[drewfustini]

In summary, it works as expected.

[drewfustini]

OpenOCD using psoc4.cfg  for CCG3PA and FT2232H adapter: FAILURE

The Tigard is an interface board with the FTDI FT2232H.  It uses tigard-swd.cfg which is as follows:

adapter driver ftdi
transport select swd
ftdi_vid_pid 0x0403 0x6010
ftdi_channel 1
adapter speed 2000
ftdi_layout_init 0x0018 0x05fb
ftdi_layout_signal SWD_EN -data 0
ftdi_layout_signal nSRST -ndata 0x0020 -noe 0x0040

I have wired the SWD pins on the Tigard to the the MiniProg header on the CCG3PA EVK main board.  I have also attached the Salaea Logic probes to the SWD pins. See attached photo.

Just like with the PSoC 4200M, I used this command:

openocd -f ~/tigard-swd.cfg -f ./tcl/target/psoc4.cfg -c " init; exit"

However, it fails to connect to the target:

openocd -f ~/tigard-swd.cfg -f ./tcl/target/psoc4.cfg -c " init; exit"
Open On-Chip Debugger 0.10.0+dev-gd526e667d-dirty (2021-02-10-23:02)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
Info : FTDI SWD mode enabled
adapter speed: 1000 kHz
adapter speed: 2000 kHz
** Test Mode acquire not supported by selected adapter
cortex_m reset_config sysresetreq
START WITH CONFIGURE
START WITH flash bank
START WITH add_verify_range
Info : clock speed 2000 kHz
Error: DAP 'psoc4.cpu' initialization failed (check connection, power, etc.)
Info : psoc4.dap: powering down debug domain...
Warn : Failed to power down Debug Domains

Salaea Logic shows 2MHz clock is visible and Line Reset is visible on data pins.  See the screenshots.  Unfortunately, I can not figure out why the sequence does not proceed beyond Line Reset to Debug Port request for IDCODE.

I would appreciate any insights or suggestions anyone might have.  Thank you!