[CCG3PA] Apple Charging

[Ivan_Lee]

Please refer to below application note that describe about - "Apple Charging 2.1 A - The Apple charger (HX3) holds its D+ line at 2.7 V and D- line at 2 V"

Implementing Battery Charging Features Using HX3 (infineon.com)

customer has a question about D+ voltage level for Apple Charging 2.1 A using CCG3PA.

how to increase D+'s voltage to meet 2.7V for apple charging by firmware ? now level is under 2.7V

[Neo_Qin · Accepted solution]

Hi @Ivan_Lee ,

The latest version of Infineon EZ-PD™ CCGx Power Software Development Kit can support Apple charging 2.4A , since Apple 2.1 and Apple 2.4 both support the 2.7V voltage on D+, it's recommended that end customer use the CYPD3171-24LQXQ_cla project in the SDK for D+ voltage verification, which intended to work on the CY4532 EZ-PD™ CCG3PA Evaluation Kit.

Based on the usage model of the D+/D- lines, the source charging protocol can be divided into Apple charging and BC 1.2 based (BC 1.2 DCP, QC, and AFC). Default CCG3PA firmware allows only one of the two modes of operation.

Please use the USB EZ-PD™ Configuration Utility to generate a config.c file which has the Apple 2.4A termination option enabled.

1) Configuration for enabling Apple 2.4A charging only:

2) If the end customer wants to support Apple 2.4A source charging protocol along with other BC 1.2 based protocols, it requires external resistance based Apple termination. More details please refer to "Chapter 4.8_Legacy/proprietary charging configurations" of the "Cypress EZ-PD™ CCGx Power SDK User Guide_Revision 3.5",  I have attached it for your convenience.

Regards,

Neo

[Ivan_Lee]

Hi, Neo,

what value is external resistance do you suggestion to use for Apple 2.4A + BC1.2?

becuase currenly the D+ is lower than 2.7V 

[Neo_Qin]

Hi @Ivan_Lee ,

This is detailed in the "Chapter 4.8_Legacy/proprietary charging configurations" of the "Cypress EZ-PD™ CCGx Power SDK User Guide_Revision 3.5", I quote as follow:

The hardware should be modified to have a dedicated GPIO connected to D+ line of the port via a resistance (each port requires a different GPIO and resistor). The user can choose to enable this only on one port. The resistance value to be used is based on the VDDIO voltage supplied to the CCG3PA device. If the device is powered via internal regulator or if the VDDD is supplied with 3.3V, then the resistance to be used is 5.1KOhm. If the device is powered via 5V VDDD, then the resistance value to be used is 18KOhm. High precision resistance should be used for accurate functioning.

Regards,

Neo