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USB EZ-PD™ Type-C Forum Discussions

MaGa_3860551
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Level 1
Welcome!

Hello,

We are using the CCG3 CYPD3125-40LQXIT with a custom notebook firmware based on the notebook example of the SDK 3.2.1, and we're having some strange behavior when powered by the USB-C. Our board have a consumer role with a VBUS at 20V. When our board is off, only the CCG3 is powered, from the VBUS. When the board is on, all the board is powered from the USB-C VBUS and the CCG3 is powered from its VSYS. When the board is powered down, the VSYS of the CCG3 is lost and the CCG3 is only powered from the VBUS. At this moment, an over-voltage is detected by the CCG3 and the port is reset. The VBUS is lost and the CCG3 shuts down. This wasn't expected.

I have probed the VBUS with an oscilloscope and I can't see any over-voltage. The maximum overshoot seems to be 500mV. The OVP Threshold parameter is at 20% in the configuration, so it should not trigger an OVP. I see that there are the "Debounce period" and "Retry count" parameters in the Over Voltage Protection section of the configuration, but these parameters can't be changed for the CCG3. These parameters can't be increased to see if it has an effect.

Our CCG3 firmware also controls the board power with a GPIO. It shows the same behavior as when the power is removed without interaction of the CCG3 (described above). But, if a delay of 15ms or more is added after toggling this GPIO to power down the board (delay added with the function CyDelay), no over-voltage is detected, the CCG3 switches from VSYS to VBUS and it continues to operate as expected.

Any ideas of why OVP is triggered in some conditions and not with a delay in CCG3 firwmare? And how could I prevent an OVP when powering down the board?

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1 Solution
RajathB_01
Moderator
Moderator
Moderator
250 replies posted 100 replies posted 50 replies posted

Resolution summary:

- Schematic review: No problems found

- Attempt at reproducing the issue: Unsuccesful

- Workaround: Existing workaround of delay seems appropriate

- Further investigation: Requires debugging with the actual board sample and firmware

Please open a new thread as discussed in order to avail more support or if you want to update us about anymore issues.

Regards,

Rajath

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3 Replies
RajathB_01
Moderator
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Moderator
250 replies posted 100 replies posted 50 replies posted

Hi,

Can you please share your board schematics and also VBUS waveforms?

Regards,

Rajath

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Hi,

I have observed two cases on the VBUS, one with more voltage variation and one with less variation. The VBUS behaves the same way if the CCG3 resets or if it doesn't reset by adding a delay.

Our board schematics are very similar to the DRP Application Diagram example in the datasheet or the CY4531 evaluation kit. I have sent you a direct message with our schematic.

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RajathB_01
Moderator
Moderator
Moderator
250 replies posted 100 replies posted 50 replies posted

Resolution summary:

- Schematic review: No problems found

- Attempt at reproducing the issue: Unsuccesful

- Workaround: Existing workaround of delay seems appropriate

- Further investigation: Requires debugging with the actual board sample and firmware

Please open a new thread as discussed in order to avail more support or if you want to update us about anymore issues.

Regards,

Rajath

0 Likes