TRAVEO™ T2G Forum Discussions

Hi Infineon team,

I'd run chip CYT3BB7CEBQ0AESGST using SDL 7.7.

I boot the CM0 chip using the Boot folder from SDL. 

Configure:

System init clock in file system_tviibh4m_cm0plus.c (sample with ECO=16MHz).

I using external crystal 8MHz (ECO = 8MHz). So I just changed CY_SYSTEM_PLLx_CONFIG_REFDIV, CY_SYSTEM_PLLx_CONFIG_FEEDBACKDIV, CY_SYSTEM_PLLx_CCONFIG_OUTDIV

to get PLL0 = 250 MHz

#define CY_SYSTEM_PLL0_CONFIG_REFDIV (2UL)
#define CY_SYSTEM_PLL0_CONFIG_FEEDBACKDIV (125UL)
#define CY_SYSTEM_PLL0_CONFIG_OUTDIV (4UL)

PLL1 = 196607999.92Hz

#define CY_SYSTEM_PLL1_CONFIG_REFDIV (1UL)
#define CY_SYSTEM_PLL1_CONFIG_FB_INT (98UL)
#define CY_SYSTEM_PLL1_CONFIG_FB_FRAC (5100273UL)
#define CY_SYSTEM_PLL1_CONFIG_OUTDIV (4UL)

PLL2 = 160MHz

#define CY_SYSTEM_PLL2_CONFIG_REFDIV (1UL)
#define CY_SYSTEM_PLL2_CONFIG_FEEDBACKDIV (40UL)
#define CY_SYSTEM_PLL2_CONFIG_OUTDIV (4UL)

PLL3 = 80MHz

#define CY_SYSTEM_PLL3_CONFIG_REFDIV (2UL)
#define CY_SYSTEM_PLL3_CONFIG_FEEDBACKDIV (80UL)
#define CY_SYSTEM_PLL3_CONFIG_OUTDIV (4UL)

Clock HFx:

Issues:

I use SDL API:

It seems to be OK. But when I run CM0 will reset and can't jump to CM7_0. 

If I reduce all PLL output clocks by half -> CM0 and CM7_0 run normally (but the clock is 1/2 smaller than desired)

If I use external crystal 16MHz and the default file system_tviibh4m_cm0plus.c things ok (CM0 and CM7_0 run normally).

Questions:

1. I think refdiv, feedbackdiv, and output are ok following the restrictions of the datasheet (Infineon-TRAVEO_T2G_CYT3BB_4BB-DataSheet-v09_00-EN.pdf).

But why chip can't run as expected?

2. Do I need to edit other values such as ROM/RAM waitstate and FLASH wait cycle?
If yes then what should the value be I can't find the reference.

Please help me to resolve these issues (Refer to file system_tviibh4m_cm0plus.c for more detail).

Thank you Infineon team.

<Question>

Does the Supervisory region (SFlash) area of CYT4BF support ECC?
If it support ECC,
Are the registers that control ECC common to FLASHC/FLASHC1_FLASH_CTL.MAIN_ECC_EN ?
(Please see T2G-B-H Architecture TRM,8.2.2.5 Code Flash ECC, Table 8-6. Flash ECC Enable Registers)

If it does not support ECC,
Please tell me why it is not support with ECC.or Is there any other monitoring function?

Thank you for your support.

<質問>
CYT4BFのSFlash領域はECCに対応していますでしょうか？
ECCに対応している場合、
8.2.2.5 Code Flash ECCに記載の、FLASHC/FLASHC1_FLASH_CTL.MAIN_ECC_ENのようなECCを制御するレジスタはありますでしょうか？
（T2G-B-H Architecture TRM, Table 8-6. Flash ECC Enable Registers参照）

・ECCに対応していない場合、
ECCに対応していない理由を教えてください。もしくはECC以外の監視機能はありますでしょうか？

よろしくお願い致します。

Hello Infineon Team, 

ICU Elapsed time API is not reading properly during low frequency input signal. such as (10 HZ to 130 HZ) but the tick values are providing correctly for above 130 HZ input frequency Please find the configuration details here. 

Channel Tick Frequency -   8 MHZ of ICU Channel

Clock Reference Point Frequency - 16 MHZ

PClock frequency - 80 MHZ  

Kindly let me know is there any limitations in the input signal. or should I modifications in clock configurations?  

Hello,

We would like to use the low power mode of the CYT2B73. eco We have connected an external crystal of 16MHZ, do we need to connect an external low frequency crystal to the WCO pin and then configure it through software?

After checking the DEMO file for the MUC, it doesn't have WCO connected to it, but only the ECO pin does it enable low power mode?

For SLEEP and DEEPSLEEP mode what is the difference between the two?

If you go to low power, are the clocks all off and how do you wake up the MCU?

Above.

Thank you~

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/TRAVEO-T2G/CYT2B73%E7%9A%84%E4%BD%8E%E5%8A%9F%E8%80%97%E4%B8%8E%E6%97%B6%E9%92%9F%E6%99%B6%E6%8C%AFECO-amp-WCO/td-p/738107

Hello Experts,

I was able to work with Evaluation board (TRAVEO II T2G KIT_B_E_LITE) which has MCU of CYT2BL5CAA using IAR workbench.

I used the T2G_Sample_Driver_Library_7.9.0\tviibe4m for initial configuration and i could see the LEDs are blinking.

I have a custom board which uses CYT2b95CAC chipset. I tried using the same configuration has of evaluation board(CYT2BL5CAA) and changed the only LED port pins, Flashing was successful but unfortunately no LEDs were blinking.

FYI.. I am using tviibe4m_flash_cm0plus_template from T2G_Sample_Driver_Library_7.9.0\tviibe4m\tools\iar\flash

My questions are 

1. Can i use the IAR workbench template of CYT2BL5CAA to CYT2b95CAC controller( both are dual core).

2. Is there any specific configuration i need to follow for this CYT2b95CAC.

3. I am suspecting Oscillator configuration needs to be tuned as in custom board we are using 20Mhz crystal whereas in evaluation board it was 16Mhz.

Thanks

Kiran

Hi All,

What will be the status of CPUSS_DP_STATUS register in Traveo II BH after executing TransitionToSecure whether the 
CPUSS_DP_STATUS.SWJ_CONNECTED will be set to not active?

I am trying to reenable the DAP protection after TransitionToSecure so I am writing CPUSS_AP_CTL registers to enable the AP_CTL registers. I need to know how to confirm JTAG is enabled?
Whether the status will be reflected in CPUSS_DP_STATUS register?