Hi,
I'm using IAR（version : 8.42.1） to build a Traveo II CYT2B9 project（tviibe1m_flash_cm0plus_template.eww demo project）, but I found the built code address is not aligned, which can cause the cortex-m0 enter the fault, how should I solve this problem?
Hi pengzw,
You can check with the following debugger capture view, actually the code is aligned on a memory address multiple of 2 (align 2).
Besides also attached our map and lst file for your reference.
Thanks,
Hi pengzw,
Sorry for the late response, I got the same map file as you, but no idea why the map file show the function started at 0x1000'0d55 not align to 2 byte, we might need to check with debugger, will get back to you as soon as possible.
Thanks,
Hi pengzw,
You can check with the following debugger capture view, actually the code is aligned on a memory address multiple of 2 (align 2).
Besides also attached our map and lst file for your reference.
Thanks,
Thank you for your reply !
I re-checked the failure, it wasn't caused by an unaligned address access.
The reason is that I chose the device version incorrectly, which caused the program to crash in the "InitRamEcc" function.
The problem of the chip crashing has been solved. But there is still some knowledge about the ARM processor that I have to contiune study.
Thank you !
Hi, @Alfred_Tsang
Initially, what confused me is that the address where the "BLX" instruction jumps to is unaligned, as show below.
The image below has answered part of my questions.
Hi pengzw,
Sorry for the long wait.
For the different address between map file and the program counter (PC),
I believe the reason because of the PC should not return an odd number address, when you write to PC, LSB of value is loaded into the EPSR T-bit.
In order words, you can only find the value of PC register is an even number.
For more information, please refer to 'Cortex-M4 Technical Reference Manual'and'Cortex-M4 devices Generic User Guide'
Thanks,
