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Traveo II CYT4B can run on 350MHZ? code is as follow:
#if (CY_SYS_PLL400M_0_FREQ == CY_SYS_PLL400M_0_350MHz)
// PLL_OUT = 24,000,000(Feco) / 3 * 125 / 5 = 200,000,000Hz
// Restriction: 400,000,000 <= Fvco <= 800,000,000
// This time, Fvco = 16,000,000 * 175 / 4 = 700,000,000.
#define CY_SYSTEM_PLL0_CONFIG_REFDIV (2UL)
#define CY_SYSTEM_PLL0_CONFIG_FEEDBACKDIV (175UL)
#define CY_SYSTEM_PLL0_CONFIG_OUTDIV (6UL)
/*
#define CY_SYSTEM_PLL0_CONFIG_REFDIV (3UL)
#define CY_SYSTEM_PLL0_CONFIG_FEEDBACKDIV (125UL)
#define CY_SYSTEM_PLL0_CONFIG_OUTDIV (5UL)
*/
#elif (CY_SYS_PLL400M_0_FREQ == CY_SYS_PLL400M_0_320MHz)
Solved! Go to Solution.
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Traveo II CYT4B 350M
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Hello,
According to Clock Diagram (Figure 7-1) or below table, CM7_0 is sourced from CLK_HF1, which is selected from PLL400#0 (out: 350MHz) in SDL 6.6 example (by default). Kindly review system_tviibh8m_cm0plus.c included in SDL and Chapter 18 of Clock System of Traveo II Body High Architecture TRM for more details.
//CYT4BF datasheet
Best regards,
Amy
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Hi,
This looks a questioning discussion, so it is moved from Code Example board to the current Traveo II board, this way the question could be caught by Traveo II community members faster.
P.S. Welcome to share your code(if any) as example with community members here when you want.
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Hello,
According to Clock Diagram (Figure 7-1) or below table, CM7_0 is sourced from CLK_HF1, which is selected from PLL400#0 (out: 350MHz) in SDL 6.6 example (by default). Kindly review system_tviibh8m_cm0plus.c included in SDL and Chapter 18 of Clock System of Traveo II Body High Architecture TRM for more details.
//CYT4BF datasheet
Best regards,
Amy