TRAVEO™ T2G Forum Discussions

Hii,

I'm using CYTVII-C-2D-6M-327-SET evaluation kit for my project.   I require information's about pinout details exposed out in dev kit and its schematic diagram .

I couldn't get those documents.  could you support on this ?

Thanks.

we are trying to re flash the Micro Via MODUS tool .it is getting heat while flashing after 60% completed. and our tool shows power interrupt .

Error Image from our flashing tool:

please support to resolve this issue. we are struggling to Re flash the Micro . kindly share your input to resolve the issue.

Hi,

 I am having the Traveo-T2G kit. CYTVII-2D-4M-216 set and the CYT3DLABHBES  cpu.

I am running the TRAVEO T2G Sample driver Library provided by infineon. I want to use freeRTOS in the project.

Previously I was using IAR V9.30.1 , in that version I could see the option in workspace to switch to the RTOS supported workspace.

Now I am using IAR v8.22.2, here no option in workpace for RTOS. Can somebody help me to run RTOS example.

Hi, I'm using CYT4BF.

I confirmed that the Bandgap Reference circuits can be set to higher current mode or low power in the PWR_CTL2.BGREF_LPMODE register.

1) Can you explain in more detail the higher current mode and low power mode of Bandgap Reference circuits?
2) Can you tell me in what cases the PWR_CTL2.BGREF_LPMODE register is used?

BR.

taegyunahn.

Hi expert.

Recently, I encountered a case where the SFlash of the CYT2B75CAS chip was abnormally modified;

The chip abnormality manifests itself in the form of failure to boot from power-up, connecting to the chip through the compiler Attach to running targe mode, and then reading the data in the SFlash area of the chip;

And compared with the other two normal chips, found that the abnormal chip SFlash area has a lot of data is not the same, the difference area is mainly in the paragraph Flashboot code and Patches; attached is the SFlash area data I saved, and the 3 chips are the same batch;

Rather strangely, the code does not contain any calls to the API interface for modifying the SFlash, only the Erase Code Flash and Work Flash code;

What could cause the SFlash area of the chip to be abnormally modified? Regarding the area 0x17001C00 ~ 0x17006FFF, can it be abnormally tampered with when the chip is in Normal mode?

Please help the experts to analyze the possible reasons why SFlash is being modified abnormally;

Thank you~~

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Hi Team,

Couldn't find the CAN Mailbox definitions in SDL Libraries. Is there a way to configure the mailbox in TRAVEO 2 CYT2CL?

Thanks,
Pradeep

Hi,

I want to know CYT2B75CAE this controller is supporting AUTOSAR, If yes where i will get those information,

when i browse i am not able to find the information

Hello Experts,

I am referring this document (page 36) for my configuration of UART to 115200 baudrate. I am not getting desired output on my putty terminal(I can see continuous junk getting displayed)

https://www.infineon.com/dgdl/Infineon-AN225401_How_to_Use_Serial_Communications_Block_(SCB)_in_Traveo_II_Family-ApplicationNotes-v05_00-EN.pdf?fileId=8ac78c8c7cdc391c017d0d3e657867d2

FYI.. This is my Cy_SysClk_PeriphSetFracDivider function settings.

CLK_PERI Frequency external crystal = 20MHz
115200(baud rate) * 16(OVS) = Input Clock = 1843200 Hz

DIV24.5 = 20MHz / 1843200 = 10.8506

Fractional Divider
Integer : 10 , Fractional : 27 (0.8437 = 27/32)

I have one basic doubt is CLK_PERI freq is same as external crystal oscil(ECO) 

Does modustoolbox support CMSIS-DAP for debugging TRAVEO II, and if so, how do I set it up?

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