TRAVEO™ T2G Forum Discussions
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/TRAVEO-T2G/CYT2B7-can-id-filter%E8%AE%BE%E7%BD%AE%E6%8C%87%E5%AE%9Aid-0x7A1-%E4%B8%8D%E8%83%BD%E8%AF%86%E5%88%AB-%E4%BD%86%E8%AE%BE%E7%BD%AE%E4%B8%BA0xA1%E5%8F%AF%E4%BB%A5%E6%AD%A3%E5%B8%B8%E8%AF%86%E5%88%AB-%E6%98%AF%E5%90%A6%E5%AF%B9id%E6%9C%89%E9%99%90%E5%88%B6-%E5%8E%9F%E5%9B%A0%E6%98%AF%E4%BB%80%E4%B9%88/td-p/685896
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The code is as follows, the DMA can't transfer data, but it enters the interrupt the moment it is triggered by the software, and it can't enter the interrupt again
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/TRAVEO-T2G/CYT4BB%E5%8D%95%E7%89%87%E6%9C%BADMA%E4%B8%8D%E8%83%BD%E4%BC%A0%E8%BE%93%E5%8D%B4%E5%BC%82%E5%B8%B8%E8%BF%9B%E5%85%A5DMA%E4%B8%AD%E6%96%AD/td-p/688790
Show LessThe ADC is triggered with tcpwm, the ADC triggers the dma. 2048 points are captured and transported into the interrupt. The time interval to enter the interrupt is about 250ms, the target array is 16 bits, and the datasize is 16 bits. If srcTxfrSize is set to 1, the time to enter interrupt will be shortened to 150ms. If I replace the ADC result register with a 16-bit array as the source array and set srcTxfrSize to 0, the time to enter interrupt will be 250ms, how to solve this problem? Thank you for your help.
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/TRAVEO-T2G/cyt4bb-DMA%E4%BC%A0%E8%BE%93%E6%97%B6%E9%97%B4%E5%BC%82%E5%B8%B8/td-p/690170
Show Lesssmartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/TRAVEO-T2G/CYT2B73-%E4%BD%BF%E7%94%A8greenhills%E7%BC%96%E8%AF%91%E5%99%A8%E6%97%B6-%E6%97%A0%E6%B3%95%E5%B0%86%E6%95%B0%E7%BB%84%E5%90%8D%E5%BC%BA%E5%88%B6%E8%BD%AC%E6%8D%A2%E4%B8%BA%E5%87%BD%E6%95%B0%E6%8C%87%E9%92%88-%E5%BA%94%E5%A6%82%E4%BD%95%E8%A7%A3%E5%86%B3/td-p/687609
Show LessTo write data to flash on Traveo 2 processors, a sector erase must be performed first, but when performing a sector erase, a 32-bit address is cleared. Even if I wanted to print an 8-bit value, I would waste the life of the 32-bit address. For this reason, I want to use Flash EEPROM emulation. Is there a source file for this?
Show LessI found that in the CYT 4B CM0 core, the timer interrupt cannot be used to CPUIntIdx0_IRQn to the CPUIntIdx2_IRQn, otherwise the interrupt cannot be entered, please why
Show LessHello, I need to trigger the ADC with TCPWM, the ADC is triggering the dma, transmitting 2048 points, and the sampling frequency is 8Khz. The problem is that when DMA srcTxsize is set to 32bit, it originally took 266ms to collect 2048 points, but now it only takes 160ms, which is not normal, because I use a timer to sample at equal intervals, and when srcTxsize is set to 16bit, it is 266ms (I will change the number of bytes and datasize of the array accordingly), and I found that changing the division coefficient of the timer clock will cause DMA to not be transmitted. I suspect there's something wrong with the clock. Below is my system configuration code, and ADC, DMA, TCPWM configuration code.
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