TRAVEO™ T2G

Hi ,

Is it possible to create a single hex file from two different srec files  that can be used to to flash the Bank A and Bank B  in a single command using miniprog ? 

Regards

Gokul

在CYT2B95CA的板子上调试ADC采样时，发现输入信号经过Π型滤波网络后，电压有明显的压降；

datasheet中给出了导通电阻；

按照如下图所述的ADC输入网络，在 ADC输入<0.4V 或 >4.2V时，输入信号经过R2后有明显的压降，压降范围在0.1V~0.2V；

如果有R2阻值改成1K，压降明显变小；

如果参考手册给出的ADC导通阻值，外部电阻远大于导通电阻，理论上不会出现压降；

那在不考虑PCB Layout 阻抗的情况要，要如何设计匹配网络，保证ADC输入阻抗匹配呢？

目前我们使用这个Π型网络，电阻，电容值要调整成多大才能保证输入线路上不会有明显的压降呢？

期待你的答复，谢谢~~

Hi, 

Going thoroughly through CYT4BF datasheets and TRM, I see that the MCU has 2 M_TTCAN controller with 5 channels each. What are the limitations of such an arrangement? Typically, MCUs use a 1:1 mapping controller to channel. 

Basically I'm looking to answer these questions:

1. Does this arrangement have any hidden limitations that are not clear?

2. Can all channels operate independently at a different bit rate at full CAN-FD capacity of 5Mbps at the same time (that is - all 5 channels connected to active peripherals operating full speed of 5Mbps at the same time)?

3. If there are shared functions that cause performance impacts, what are they?

Thank you for your support!

Vai

Hi

Good day.

I have a questions about single/dual bank selection on Traveo II.

We are based on programming guide to implement the programming algo.

it doesn't mention about bank selection, and it is mapped the single bank.

My question is..

if customer need to load the image file to dual bank mapping, do we need to bank selection option to set FLASHC_FLASH_CTL? or we don't need to do anything, and the device will do the bank setting after it is booted.

There is customer's requirement. You can see the file B setting. and How do we do? 

Thank you.

Jack

Hi

I am trying to do some AXI DMA operation to transfer the data between two locations.

The code that does the AXI DMA Configuration and triggers the operation resides in CM7_0.

After triggering the transfer, I am getting the DESTINATION BUS ERROR.

What does this mean? Also how do we debug this issues?

How is this AXI DMA different from normal DMA. Is it only the speed?

DMA Config:

• Both Source\Destination address are in SRAM.
• 1D Array transfer.

Thanks In Advance!