Is it possible to create a single hex file from two different srec files that can be used to to flash the Bank A and Bank B in a single command using miniprog ?
按照如下图所述的ADC输入网络，在 ADC输入<0.4V 或 >4.2V时，输入信号经过R2后有明显的压降，压降范围在0.1V~0.2V；
那在不考虑PCB Layout 阻抗的情况要，要如何设计匹配网络，保证ADC输入阻抗匹配呢？
Going thoroughly through CYT4BF datasheets and TRM, I see that the MCU has 2 M_TTCAN controller with 5 channels each. What are the limitations of such an arrangement? Typically, MCUs use a 1:1 mapping controller to channel.
Basically I'm looking to answer these questions:
1. Does this arrangement have any hidden limitations that are not clear?
2. Can all channels operate independently at a different bit rate at full CAN-FD capacity of 5Mbps at the same time (that is - all 5 channels connected to active peripherals operating full speed of 5Mbps at the same time)?
3. If there are shared functions that cause performance impacts, what are they?
Thank you for your support!
When using the license key received for the UART & I2C plugins from your side.
The key seems to be activated on the EB Client license administrator but when adding those plugins to tresos, it gives an invalid license message.
Here is the response from EB side when I created a ticket regarding this issue.
It's just a license to open Eb Tresos Studio, to enable 3rd party MCAL from Cypress I suspect another additional license is required.
Please contact Cypress for further support.
I wrote this issue in the d
The license is working on other machines but it’s not working on my machine.
Error messages are attached.
I have a questions about single/dual bank selection on Traveo II.
We are based on programming guide to implement the programming algo.
it doesn't mention about bank selection, and it is mapped the single bank.
My question is..
if customer need to load the image file to dual bank mapping, do we need to bank selection option to set FLASHC_FLASH_CTL? or we don't need to do anything, and the device will do the bank setting after it is booted.
There is customer's requirement. You can see the file B setting. and How do we do?
There seems to be a difference in the initial state of the input buffer between the following two. Which one is correct?
2.1. What is the status of unused GPIO pins?
The default mode is High-Z, input buffer is enabled, and no internal pull-up/down resister connected.
T2G Body Entry Arch TRM (002-19314 Rev. *H)
22.6.1 Drive Modes -> High-Impedance
High-impedance drive mode with input buffer disabled is also the default pin reset state.
Best regards,Show Less
I have a question about eSHE/HSM.
The datasheet mentions the eSHE/HSM options, and it is supported by third party.
May i know how to implement the options?
In addition, we are third party programmer manufacturer.
Do we need to implement it on our programming algo? if yes, how to do this?
Our customer needs the HSM programming requirement, and it seems to be defined to TOC2 area in Sflash. Is it correct?
I am trying to do some AXI DMA operation to transfer the data between two locations.
The code that does the AXI DMA Configuration and triggers the operation resides in CM7_0.
After triggering the transfer, I am getting the DESTINATION BUS ERROR.
What does this mean? Also how do we debug this issues?
How is this AXI DMA different from normal DMA. Is it only the speed?
Thanks In Advance!