TRAVEO™ T2G Forum Discussions
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I am running the gfx_env - flexible mode example from the "Traveo Sample driver library".
It outputs following image
(**They just enabled the test image once and then they are only updating the test pattern in the External RAM periodically. )
Where they kept this image RAM/ROM?. If I want to show any other images of my own, will I able to do that?.
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Hi
I'm using CYT2B9.
I want to know how to enable and disable SCB UART FIFO.
I am either Enable or Disable UART RX Interrupt depending on the situation.
When data input occurs when UART RX Interrupt is disabled, an interrupt does not occur, but it appears that an update is performed on the FIFO. (Interrupt : X / FIFO update : O)
So, there is a problem where an interrupt occurs immediately when UART RX Interrupt enable is performed due to FIFO update.
To solve this problem, I am currently using the method of enabling UART RX Interrupt after clearing the RX FIFO.
Q) Is there a way to enable or disable SCB UART FIFO? (It could not be confirmed in Register TRM.)
BR
taegyunahn.
Show LessHello.
Please advise if there are any code routines for all four use cases in this document. AN226043 - How to use sound subsystem in TRAVEO T2G family
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/TRAVEO-T2G/Sound-subsystem-in-TRAVEO-T2G/td-p/717156
Show LessCurrently I am working I2C communication implementation in that I keep master as a TRAVEO and slave as a external EEPROM ATMT0730, which has the address is 0xA0. but the address is does not satisfied with driver file condition.
For example I will take the slave address of EEPROM as 0xA0, which is compared to 0x80 in driver file. here I mention below
(0UL==((0xA0)&(0x80))
the above condition does not satisfied.
and also I attached the snipped for your reference.
Show LessI am currently using traveo t2g BH4mb mctlr and have a requirement to enable and disable JTAG on conditionla basis instead of permanently disabling the same.
i have planned to set the lifecycle stage to Secure and also give secure restrictions if failed
My question is :-
Does the mctlr have an existing provision to enable and disable JTAG based on the authentication of Secure_Hash calculated for the Sflash contents based on any UniqueID present in the board and not publicly accessible?
Also at what address can the efuse bit for the AP_CM7/AP_CM0 cores can be set?
FYR,
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Hi,
I am having the Traveo-T2G kit. CYTVII-2D-4M-216 set and the CYT3DLABHBES cpu.
I am running the TRAVEO T2G Sample driver Library provided by infineon.
Is freeRTOS supported for this MCU ?. Because when running the example of freertos from "tviic2d4m". I am getting error ike the FreeRTOS.h was not found. Then I found that the freeRTOS path is not included in the workspace. Can I add manually?.
*Note: In the IAR workspace tviic2d4m_flash_cm7_0_mc_template -> the RTOS folder is excluded from build.
Hello!
I have a CYT3DLABABQ1AES board and after flashing the CodeFLASH and WorkFLASH and SFLASH area programs. I erased the data in CodeFLASH and WorkFLASH area and power off, now I can't rewrite the data in CodeFLASH and WorkFLASH area.
I'm using jlink, now connect and read are successful, but I can't erase and burn, I'd like to ask if there's any way to re-write the CodeFLASH and WorkFLASH area data into it?
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/TRAVEO-T2G/CYT3DL/td-p/705749
Show LessI am currently working on software development in the following environment:
Evaluation Board: CYTVII-B-H-8M-320-CPU
Debugger: I-Jet
Development Environment: IAR embedded workbench v9.30.1
I am implementing FreeRTOS using the Sample Driver Library source code. However, I have noticed that when I perform a "hardware reset" during debugging, it leads to a hard fault. I am curious to know the reason behind this hard fault occurrence. Could you please provide any insights or suggestions?
Best regards,
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